w83977atf Winbond Electronics Corp America, w83977atf Datasheet - Page 151

• Manufacturer Part Number: w83977atf
• Description: Winbond I/o
• Manufacturer: Winbond Electronics Corp America

CRF3 (WDT_CTRL0, Default 0x00)
CRF4 (WDT_CTRL1, Default 0x00)
*Note: 1). Internal logic provides an 1us Debounce Filter to reject the width of P20 pulse less than 1us.
11.10 Logical Device 9 (GP I/O Port III)
CR30 (Default 0x00)
CR60, CR 61 (Default 0x00, 0x00)
CR62, CR 63 (Default 0x00, 0x00)
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Bit 7 - 4: Reserved
Bit 3: When Time-out occurs, Enable or Disable Power LED with 1 Hz and 50% duty cycle output.
Bit 2: Mouse interrupt reset Enable or Disable
Bit 1: Keyboard interrupt reset Enable or Disable
Bit 0: Reserved.
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Bit 7 - 4: Reserved
Bit 3: Enable the rising edge of Keyboard Reset(P20) to force Time-out event, R/W*
Bit 2: Force
Bit 1: Enable Power LED 1Hz rate toggle pulse with 50% duty cycle , R/W
Bit 0:
Bit 7 - 1: Reserved.
Bit 0: = 1 Activates the logical device.
These two registers select GP3 I/O base address [0x100:0xFFF] on 1 byte boundary.
These two registers select GP32 alternate function Primary I/O base address [0x100:0xFFE] on 2-
byte boundary; they are available as you set GP32 to be an alternate function (General Purpose
Address Decode).
2). The P20 signal that coming from Debounce Filter is ORed with the signal generated by the Force Time-out bit and then
Watch Dog
= 1 Enable
= 0 Disable
= 1
= 0
= 1
= 0
= 1 Enable
= 0 Disable
= 1 Force
= 1 Enable
= 0 Disable
= 1
= 0
connect to set the Bit
= 0 Logical device is inactive.
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Timer Control Register #0
Timer Control Register #1
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Timer Status, R/W
Timer is reset upon a Mouse interrupt
Timer is not affected by Mouse interrupt
Timer is reset upon a Keyboard interrupt
Timer is not affected by Keyboard interrupt
Timer time-out occurred.
Timer counting
0(Watch Dog
Timer Time-out, Write only*
Timer time-out event; this bit is self-clearing.
Timer Status). The ORed signal is self-clearing.
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Publication Release Date:April 1998
W83977ATF
PRELIMINARY
Revision 0.52