w83977atf Winbond Electronics Corp America, w83977atf Datasheet - Page 56

no-image

w83977atf

Manufacturer Part Number
w83977atf
Description
Winbond I/o
Manufacturer
Winbond Electronics Corp America
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
w83977atf-AW
Manufacturer:
Winbond
Quantity:
8
Part Number:
w83977atf-AW
Manufacturer:
MIT
Quantity:
1 000
Bit 4: When this bit is set to a logical 1, the UART enters diagnostic mode by an internal loopback, as
Bit 3: The UART interrupt output is enabled by setting this bit to a logic 1. In the diagnostic mode this
Bit 2: This bit is used only in the diagnostic mode. In the diagnostic mode this bit is internally
Bit 1: This bit controls the RTS output. The value of this bit is inverted and output to RTS .
Bit 0: This bit controls the DTR output. The value of this bit is inverted and output to DTR .
This register reflects the current state of four input pins for handshake peripherals such as a modem
and records changes on these pins.
Bit 7: This bit is the opposite of the DCD input. This bit is equivalent to bit 3 of HCR in loopback
Bit 6: This bit is the opposite of the RI input. This bit is equivalent to bit 2 of HCR in loopback mode.
Bit 5: This bit is the opposite of the DSR input. This bit is equivalent to bit 0 of HCR in loopback
Bit 4: This bit is the opposite of the CTS input. This bit is equivalent to bit 1 of HCR in loopback
Bit 3: TDCD. This bit indicates that the DCD pin has changed state after HSR was read by the CPU.
3.2.4 Handshake Status Register (HSR) (Read/Write)
follows:
(1) SOUT is forced to logical 1, and SIN is isolated from the communication link instead of the
(2) Modem output pins are set to their inactive state.
(3) Modem input pins are isolated from the communication link and connect internally as DTR
bit is internally connected to the modem control input DCD .
connected to the modem control input RI .
mode.
mode.
mode.
TSR.
(bit 0 of HCR)
Aside from the above connections, the UART operates normally. This method allows the
CPU to test the UART in a convenient way.
RI and IRQ enable ( bit 3 of HCR)
7
DSR, RTS ( bit 1 of HCR)
6
5
4
3
2
-46 -
DCD .
1
0
CTS, Loopback RI input ( bit 2 of HCR)
Clear to send (CTS)
Data set ready (DSR)
Ring indicator (RI)
Data carrier detect (DCD)
CTS toggling (TCTS)
RI falling edge (FERI)
DCD toggling (TDCD)
DSR toggling (TDSR)
Publication Release Date: April 1998
W83977ATF
PRELIMINARY
Revision 0.52

Related parts for w83977atf