w83977atf Winbond Electronics Corp America, w83977atf Datasheet - Page 90

• Manufacturer Part Number: w83977atf
• Description: Winbond I/o
• Manufacturer: Winbond Electronics Corp America

If flow control is enforced when UART switches mode from MIR/FIR to SIR, then the pre-programmed
baud rate of FCBLL/FCBHL are loaded into advanced baud rate divisor latch (ADBLL/ADBHL).
4.7.2 Set5.Reg2 - Flow Control Mode Operation (FC_MD)
These registers control flow control mode operation as shown in the following table.
Bit 7~5
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
4.7.3 Set5.Reg3 - Sets Select Register (SSR)
Writing this register selects Register Set. Reading this register returns ECH.
4.7.1 Set5.Reg0, 1 - Flow Control Baud Rate Divisor Latch Register (FCDLL/ FCDHL)
Reset Value
FC_MD
Default Value
Reg.
Reg.
SSR
FC_MD2 FC_MD1 FC_MD0
FC_MD2 - Flow Control Mode
When flow control is enforced, these bits will be loaded into AD_MD2~0 of advanced
HSR (Handshake Status Register). These three bits are defined as same as AD_MD2~0.
Reserved, write 0.
FC_DSW - Flow Control DMA Channel Swap
A write to 1 allows user to swap DMA channel for transmitter or receiver when flow
control is enforced.
EN_FD - Enable Flow DMA Control
A write to 1 enables UART to use DMA channel when flow control is enforced.
EN_BRFC - Enable Baud Rate Flow Control
A write to 1 enables FC_BLL/FC_BHL (Flow Control Baud Rate Divider Latch, in
Set5.Reg1~0) to be loaded into advanced baud rate divisor latch (ADBLL/ADBHL, in
Set2.Reg1~0).
EN_FC - Enable Flow Control
A write to 1 enables flow control function and bit 7~1 of this register.
Bit 7
0
SSR7
Bit 7
1
FC_DSW
0
1
Bit 6
0
SSR6
Bit 6
1
Bit 5
0
SSR5
Bit 5
1
Next Mode After Flow Control Occurred
Bit 4
SSR4
0
Bit 4
-
- 71 -
0
Transmitter Channel
Receiver Channel
FC_DSW
Bit 3
SSR3
Bit 3
0
1
Publication Release Date:April 1998
EN_FD
Bit 2
SSR2
Bit 2
0
1
W83977ATF
EN_BRFC EN_FC
PRELIMINARY
Bit 1
SRR1
Bit 1
0
0
Revision 0.52
SRR0
Bit 0
Bit 0
0
0