w83977ctf Winbond Electronics Corp America, w83977ctf Datasheet
w83977ctf
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w83977ctf Summary of contents
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W83977EF/CTF WINBOND I/O ...
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W83977EF/CTF Data Sheet Revision History Pages Dates 1 N.A. 06/01/ 49, 50, 53, 2 06/16/98 55, 90 14, 15, 16 08/17/98 4 119, 120 09/07/ 83, 116 11/09/ ...
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Table of Contents- GENERAL DESCRIPTION..........................................................................................1 FEATURES .................................................................................................................2 PIN CONFIGURATION ...............................................................................................5 1.0 PIN DESCRIPTION..................................................................................................................... 6 1.1 HOST INTERFACE...................................................................................................................... 6 1.2 GENERAL PURPOSE I/O PORT ................................................................................................. 8 1.3 SERIAL PORT INTERFACE ........................................................................................................ 9 1.4 INFRARED INTERFACE............................................................................................................ 10 1.5 MULTI-MODE PARALLEL PORT............................................................................................... 11 ...
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... Programmable Baud Generator (BLL/BHL) (Read/Write) ..................................................... 52 3.2.9 User-defined Register (UDR) (Read/Write)........................................................................... 53 4.0 INFRARED (IR) PORTS......................................................................................54 4.1 IR PORT .................................................................................................................................... 54 4.2 CIR PORT(FOR W83977CTF ONLY) ........................................................................................ 54 4.2.1 Bank0.Reg0 - Receiver Buffer Registers (RBR) (Read)........................................................ 54 4.2.2 Bank0.Reg1 - Interrupt Control Register (ICR) ..................................................................... 54 4.2.3 Bank0.Reg2 - Interrupt Status Register (ISR)....................................................................... 55 4.2.4 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3) ...... 56 4 ...
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Bank0.Reg6 - Remote Infrared Config Register (RIR_CFG) ................................................. 58 4.2.8 Bank0.Reg7 - User Defined Register (UDR/AUDR).............................................................. 59 4.2.9 Bank1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL) ........................................................... 60 4.2.10 Bank1.Reg2 - Version ID Regiister I (VID) .......................................................................... 61 4.2.11 Bank0~3.Reg3 ...
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Bit Map of ECP Port Registers ........................................................................................... 74 5.3.12 ECP Pin Descriptions....................................................................................................... 75 5.3.13 ECP Operation................................................................................................................. 76 5.3.14 FIFO Operation................................................................................................................. 76 5.3.15 DMA Transfers................................................................................................................. 77 5.3.16 Programmed I/O (NON-DMA) Mode.................................................................................. 77 5.4 EXTENSION FDD MODE (EXTFDD) ........................................................................................ 77 5.5 ...
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COMPATIBLE PNP.................................................................................................................... 90 8.1.1 Extended Function Registers ............................................................................................... 90 8.1.2 Extended Functions Enable Registers (EFERs) ................................................................... 91 8.1.3 Extended Function Index Registers (EFIRs), Extended Function Data Registers(EFDRs) .... 91 8.2 CONFIGURATION SEQUENCE ............................................................................................... 91 8.2.1 Enter the extended function ...
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EPP Data or Address Read Cycle Timing Parameters......................................................132 11.3.5 EPP Data or Address Write Cycle Timing Parameters......................................................133 11.3.6 Parallel Port FIFO Timing Parameters..............................................................................134 11.3.7 ECP Parallel Port Forward Timing Parameters.................................................................134 11.3.8 ECP Parallel Port Reverse Timing Parameters.................................................................134 11.3.9 KBC ...
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MASTER RESET (MR) TIMING .............................................................................................148 12.7 KEYBOARD/MOUSE WAKE-UP TIMING ..............................................................................148 13.0 APPLICATION CIRCUITS ..............................................................................149 13.1 PARALLEL PORT EXTENSION FDD.....................................................................................149 13.2 PARALLEL PORT EXTENSION 2FDD...................................................................................150 13.3 FOUR FDD MODE.................................................................................................................151 14.0 ORDERING INFORMATION ...........................................................................151 15.0 HOW TO READ THE TOP MARKING ...
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... ACPI, 8042 keyboard controller with PS/2 mouse support, 14 general purpose I/O ports, full 16-bit address decoding, OnNow keyboard Wake-Up, OnNow mouse Wake-Up and OnNow CIR(W83977CTF only) Wake-Up. The disk drive adapter functions of W83977EF/CTF include a floppy disk drive controller compatible with the industry standard 82077/ 765, data separator, write pre-compensation circuit, decode logic, data rate selection, clock generator, drive interface control logic, and interrupt and DMA logic ...
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FEATURES General Plug & Play 1.0A compatible Supports 12 IRQs, 4 DMA channels, full 16-bit address decoding Capable of ISA Bus IRQ Sharing Compliant with Microsoft PC98 Hardware Design Guide Supports DPM (Device Power Management), ACPI Reports ACPI status interrupt ...
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... Infrared Supports IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps Supports SHARP ASK-IR protocol with maximum baud rate up to 57,600 bps Supports Consumer Infrared (CIR) port. (for W83977CTF only) Parallel Port Compatible with IBM parallel port Supports PS/2 compatible bi-directional parallel port ...
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... LED output, infrared I/O pins, general purpose address decoder, KBC control I/O pins OnNow Funtions Keyboard Wake-Up by programmable keys Mouse Wake-Up by programmable buttons CIR(Consumer Infra-Red) Wake-Up by programmable keys (for W83977CTF only) Package 128-pin PQFP W83977EF/ CTF Publication Release Date: March 1999 ...
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PIN CONFIGURATION 103 IRQ14/GP14 104 IRQ15/GP15 105 IOR# 106 IOW# 107 AEN 108 IOCHRDY ...
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PIN DESCRIPTION Note: Please refer to Section 11.2 DC CHARACTERISTICS for details. I TTL level bi-directional pin with 6 mA source-sink capability I TTL level bi-directional pin with 8 mA source-sink capability I ...
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Host Interface, continued SYMBOL PIN I/O DACK0# 119 IN tsu GP16 I/O 12t (WDTO) P15 I/O 12t DRQ0 121 OUT 12t GP17 I/O 12t (PLEDO) P14 I/O 12t SCI# OUT 12t DACK1# 122 IN ts DRQ1 123 OUT 12t ...
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Host Interface, continued SYMBOL PIN I/O IRQ14 103 OUT 12t GP14 I/O 12t (GPACS1#) (P17) PLEDO OUT 12t IRQ15 104 OUT 12t GP15 I/O 12t (GPACS2#) (P12) WDT OUT 12t CLKIN 1.2 General Purpose I/O Port ...
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General Purpose I/O Port ,continued SYMBOL PIN I/O PANSWIN GP23 I/O 12t (P15) CIRRX (P16) GP24 I/O 12t P13 I/O 12t SUSC (GA20) GP25 I/O 12 1.3 Serial Port Interface ...
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Serial Port Interface, continued SYMBOL PIN I/O 44 I/O 8t DTRA# PNPCSV# 51 I/O 8t DTRB# SINA 45 SINB 46 I/O 8t SOUTA PENKBC SOUTB 53 I/O 8t PEN48 47 IN DCDA DCDB# RIA# ...
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Multi-Mode Parallel Port The following pins have alternate functions, which are controlled by CR28 and L3-CRF0. SYMBOL PIN I/O SLCT FUNCTION PRINTER MODE: SLCT ...
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Multi-Mode Parallel Port, continued SYMBOL PIN I/O BUSY ACK ERR FUNCTION PRINTER MODE: BUSY An active high input ...
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Multi-Mode Parallel Port, continued SYMBOL PIN I/O SLIN INIT AFD FUNCTION PRINTER MODE: SLIN# Output line for detection ...
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Multi-Mode Parallel Port, continued SYMBOL PIN I/O STB I/O PD0 12t I/O PD1 12t I/O PD2 12t FUNCTION PRINTER ...
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Multi-Mode Parallel Port, continued SYMBOL PIN I/O 28 I/O PD3 12t I/O PD4 12t I/O PD5 12t - - 24 I/O PD6 12t - OD 12 FUNCTION PRINTER MODE: ...
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Multi-Mode Parallel Port, continued SYMBOL PIN I/O 23 I/O PD7 12t - OD 12 1.6 FDC Interface SYMBOL PIN I/O DRVDEN0 DRVDEN1 GP10 IO 12t (IRQIN1) P12 IO 12t SCI# OUT 12t HEAD# ...
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FDC Interface, continued SYMBOL PIN I/O DSA DSB MOA DSKCHG RDATA WP TRAK0 INDEX FUNCTION ...
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KBC Interface SYMBOL PIN I/O KDATA 59 I/O 16u MDATA 60 I/O 16u KCLK 67 I/O 16u MCLK 68 I/O 16u GA20 56 I/O 12t GP11 I/O 12t (IRQIN2) KBRST 57 I/O 12t GP12 I/O 12t (WDTO) KBLOCK 58 ...
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FDC FUNCTIONAL DESCRIPTION 2.1 W83977EF/CTF FDC The floppy disk controller of the W83977EF/CTF integrates all of the logic required for floppy disk control. The FDC implements a PC/AT or PS/2 solution. compatible values. The FIFO provides better system performance ...
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At the start of a command the FIFO is always disabled and command parameters must be sent based upon the RQM and DIO bit settings in the main status register. When the FDC enters the command execution phase, it clears ...
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Perpendicular Recording Mode The FDC is also capable of interfacing directly to perpendicular recording floppy drives. Perpendicular recording differs from the traditional longitudinal method in that the magnetic bits are oriented vertically. This method packs more data bits into ...
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EOT: End of Track EFIFO: Enable FIFO EIS: Enable Implied Seek EOT: End of track FIFOTHR: FIFO Threshold GAP: Gap length selection GPL: Gap Length H: Head number HDS: Head number select HLT: Head Load Time HUT: Head Unload Time ...
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Read Data PHASE R/W D7 Command W MT MFM ---------------------- C ------------------------ W ---------------------- H ------------------------ W ---------------------- R ------------------------ W ---------------------- N ------------------------ W -------------------- EOT ----------------------- W -------------------- GPL ----------------------- W -------------------- DTL ...
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Read Deleted Data PHASE R Command W MT MFM ---------------------- C ------------------------ W ---------------------- H ------------------------ W ---------------------- R ------------------------ W ---------------------- N ------------------------ W -------------------- EOT ----------------------- W -------------------- GPL ----------------------- W ...
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Read A Track PHASE R Command W 0 MFM ---------------------- C ------------------------ W ---------------------- H ------------------------ W ---------------------- R ------------------------ W ---------------------- N ------------------------ W -------------------- EOT ----------------------- W -------------------- GPL ----------------------- W ...
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Read ID PHASE R/W D7 Command W 0 MFM W 0 Execution Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- ...
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Version PHASE R/W D7 Command W 0 Result R 1 (7) Write Data PHASE R Command W MT MFM ---------------------- C ------------------------ W ---------------------- H ------------------------ W ---------------------- R ------------------------ W ---------------------- N ------------------------ ...
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Write Deleted Data PHASE R Command W MT MFM ---------------------- C ------------------------ W ---------------------- H ------------------------ W ---------------------- R ------------------------ W ---------------------- N ------------------------ W -------------------- EOT ----------------------- W -------------------- GPL ----------------------- W -------------------- ...
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Format A Track PHASE R Command W 0 MFM ---------------------- N ------------------------ W --------------------- SC ----------------------- W --------------------- GPL --------------------- W ---------------------- D ------------------------ Execution W ---------------------- C ------------------------ for Each W ---------------------- H ...
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Sense Interrupt Status PHASE R Command Result R ---------------- ST0 ------------------------- R ---------------- PCN ------------------------- (12) Specify PHASE R Command ---------SRT ----------- | --------- HUT ---------- | ...
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Relative Seek PHASE R/W D7 Command W 1 DIR -------------------- RCN ---------------------------- | (16) Dumpreg PHASE R/W D7 Command W 0 Result R ----------------------- PCN-Drive 0-------------------- R ----------------------- PCN-Drive 1 ------------------- R ----------------------- PCN-Drive 2-------------------- ...
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Sense Drive Status PHASE R/W D7 Command Result R ---------------- ST3 ------------------------- (20) Invalid PHASE R Command W ------------- Invalid Codes ----------------- Result R -------------------- ST0 ---------------------- ...
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Register Descriptions There are several status, data, and control registers in W83977EF/CTF. These registers are defined below: ADDRESS OFFSET base address + 0 base address + 1 base address + 2 base address + 3 base address + 4 ...
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HEAD (Bit 3): This bit indicates the complement of HEAD# output. 0 side 0 1 side 1 INDEX#(Bit 2): This bit indicates the value of INDEX# output. WP#(Bit 1): 0 disk is write-protected 1 disk is not write-protected DIR (Bit ...
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INDEX (Bit 2): This bit indicates the complement of INDEX# output. WP (Bit 1): 0 disk is not write-protected 1 disk is write-protected DIR#(Bit 0) This bit indicates the direction of head movement. 0 inward direction 1 outward direction 2.2.2 ...
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DRV2# (Bit 7 second drive has been installed 1 A second drive has not been installed DSB# (Bit 6): This bit indicates the status of DSB# output pin. DSA# (Bit 5): This bit indicates the status of ...
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Digital Output Register (DO Register) (Write base address + 2) The Digital Output Register is a write-only register controlling drive motors, drive selection, DRQ/IRQ enable, and FDC resetting. All the bits in this register are cleared by the MR ...
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Media ID1 Media ID0 (Bit 7, 6): These two bits are read only. These two bits reflect the value of CR8 bit 3, 2. Drive type ID1 Drive type ID0 (Bit 5, 4): These two bits reflect two of the ...
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S/W RESET (Bit 7): This bit is the software reset bit. POWER-DOWN (Bit 6): 0 FDC in normal mode 1 FDC in power-down mode PRECOMP2 PRECOMP1 PRECOMP0 (Bit 4, 3, 2): These three bits select the value of write ...
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DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC and reduced write current control. 00 500 KB/S (MFM), 250 KB/S (FM), RWC 300 KB/S (MFM), 150 KB/S (FM), RWC 250 ...
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Status Register 1 (ST1 Status Register 2 (ST2 Status Register 3 (ST3 Missing Address Mark. 1 When the FDC cannot detect the data address mark or ...
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Digital Input Register (DI Register) (Read base address + 7) The Digital Input Register is an 8-bit read-only register used for diagnostic purposes PC/ only Bit 7 is checked by the BIOS. When the register ...
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In the PS/2 Model 30 mode, the bit definitions are as follows: 7 DSKCHG (Bit 7): This bit indicates the status of DSKCHG# input. Bit 6-4: These bits are always a logic 1 during a read. DMAEN (Bit 3): This ...
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X X Bit 7-3: Reserved. These bits should be set to 0. NOPREC (Bit 2): This bit indicates no precompensation. It has no function and can be set by software. DRATE1 DRATE0 (Bit 1, 0): These two bits select ...
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UART PORT 3.1 Universal Asynchronous Receiver/Transmitter (UART A, UART B) The UARTs are used to convert parallel data into serial format on the transmit side, and convert serial data to parallel format on the receiver side. The serial format, ...
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TABLE 3-1 UART Register Bit Map Register Address Base + 0 Receiver RBR Buffer BDLAB = 0 Register (Read Only Transmitter TBR Buffer Register BDLAB = 0 (Write Only Interrupt Control ICR Register BDLAB = 0 ...
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Bit 4: EPE. This bit describes the number of logic 1's in the data word bits and parity bit only when bit 3 is programmed. When this bit is set, an even number of logic 1's are sent or checked. ...
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UART Status Register (USR) (Read/Write) This 8-bit register provides information about the status of the data transfer during communication Bit 7: RFEI. In 16450 mode, this bit is always set to a logic 0. In ...
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Handshake Control Register (HCR) (Read/Write) This register controls the pins of the UART used for handshaking peripherals such as modem, and controls the diagnostic mode of the UART Bit 4: When this bit is set ...
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Bit 7: This bit is the opposite of the DCD# input. This bit is equivalent to bit 3 of HCR in loopback mode. Bit 6: This bit is the opposite of the RI # input. This bit is ...
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TABLE 3-3 FIFO TRIGGER LEVEL BIT 7 BIT 6 RX FIFO INTERRUPT ACTIVE LEVEL (BYTES Bit 4, 5: Reserved Bit 3: When this bit is programmed to logic 1, the DMA mode ...
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TABLE 3-4 INTERRUPT CONTROL FUNCTION ISR Bit Bit Bit Bit Interrupt priority First Second Second ...
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Programmable Baud Generator (BLL/BHL) (Read/Write) Two 8-bit registers, BLL and BHL, compose a programmable baud generator that uses 24 MHz to generate a 1.8461 MHz frequency and divides divisor from the baud generator ...
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... CIR PORT(For W83977CTF only) The CIR port of the W83977CTF is an independent device, and supports an T-period mode, Over- sampling mode and Over-sampling mode with re-sync for demodulation of cir signal. Refer to the configuration registers for more information on disabling, address selecting and IRQ selectiing .The function of each CIR register is described below ...
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Bank0.Reg2 - Interrupt Status Register (ISR) Power on default <7:0> = 00000000 binary Bit Name 7-3 Reserved 2 TMR_I 1 LSR_I 0 RXTH_I Read/Write - Reserved Read Only Timer Interrupt. Set to 1 when timer count to 0. This ...
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Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3) Power on default <7:0> = 00000000 binary Bit Name 7-6 BNK_SEL<1:0> 5-4 RXFTL1/0 3 TMR_TST 2 EN_TMR 1 RXF_RST 0 TMR_CLK Read/Write Read/Write Bank Select Register. These two bits ...
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Bank0.Reg4 - CIR Control Register (CTR) Power on default <7:0> = 0010,1001 binary Bit Name 7-5 RX_FR<2:0> 4-0 RX_FSL<4:0> Table: Low Frequency range select of receiver. 001 RX_FSL4~0 Min. 26.1 00010 28.2 00011 29.4 00100 00101 30.0 31.4 00110 ...
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Bank0.Reg5 - UART Line Status Register (USR) Power on default <7:0> = 0000,0000 binary Bit Name 7-3 Reserved 2 RX_TO 1 OV_ERR 0 RDR 4.2.7 Bank0.Reg6 - Remote Infrared Config Register (RIR_CFG) Power on default <7:0> = 0000,0000 binary ...
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Bank0.Reg6 - Remote Infrared Config Register (RIR_CFG), continued Bit Name 5-4 LP_SL<1:0> 3-2 RXDMSL<1:0> 1 PRE_DIV 0 RXINV 4.2.8 Bank0.Reg7 - User Defined Register (UDR/AUDR) Power on default <7:0> = 0000,0000 binary Bit Name 7 RXACT 6 RX_PD 5 ...
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Bank1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL) The two registers of BLL and BHL are baud rate divisor and are the same as for the legacy UART port. The table below illustrates the use of the baud generator with ...
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Bank1.Reg2 - Version ID Regiister I (VID) Power on default <7:0> = 0001,0000 binary Bit Name 7-0 VID 4.2.11 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3) This register is defined same as in Bank0.Reg3. 4.2.12 Bank1.Reg4 ...
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Demodulation Block Diagram Band CIRRX Pass Filter (B.P.) Low Pass Filter Selection LP_SL<1:0> Low Pass MUX Filter Demod. 10 Block Baud Rate Sampling Clock Generator -62 - W83977EF/ CTF PRELIMINARY Demodulation Source Selection RXDMSL<1:0> 00 Sampling Shifter ...
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PARALLEL PORT 5.1 Printer Interface Logic The parallel port of the W83977EF/CTF makes possible the attachment of various devices that accept eight bits of parallel data at standard TTL level. The W83977EF/CTF supports an IBM XT/AT compatible parallel port ...
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TABLE 5-1-2 PARALLEL PORT CONNECTOR AND PIN DEFINITIONS HOST PIN NUMBER OF CONNECTOR W83977EF/CTF ...
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Data Swapper The system microprocessor can read the contents of the printer's data latch by reading the data swapper. 5.2.2 Printer Status Buffer The system microprocessor can read the printer status by reading the address of the printer status ...
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Printer Control Latch and Printer Control Swapper The system microprocessor can read the contents of the printer control latch by reading the printer control swapper. Bit definitions are as follows: Bit 7, 6: These two bits are a logic ...
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The contents of DB0-DB7 are buffered (non-inverting) and output to ports PD0-PD7 during a write operation. The leading edge of IOW# trailing edge of IOW# latches the data for the duration of the EPP write cycle. PD0-PD7 ports are read ...
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EPP Pin Descriptions EPP NAME TYPE nWrite O Denotes an address or data read or write operation. PD<0:7> I/O Bi-directional EPP address and data bus. Intr I Used by peripheral device to interrupt the host. nWait I Inactive to ...
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Extended Capabilities Parallel (ECP) Port This port is software and hardware compatible with existing parallel ports may be used as a standard printer mode if ECP is not required. It provides an automatic high burst-bandwidth channel that ...
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Data and ecpAFifo Port Modes 000 (SPP) and 001 (PS/2) (Data Port) During a write operation, the Data Register latches the contents of the data bus on the rising edge of the input. The contents of this register are ...
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Bit 7: This bit reflects the complement of the Busy input. Bit 6: This bit reflects the nAck input. Bit 5: This bit reflects the PError input. Bit 4: This bit reflects the Select input. Bit 3: This bit reflects ...
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Port Data FIFO) Mode = 010 This mode is defined only for the forward direction. The standard parallel port protocol is used by a hardware handshake to the peripheral to transmit bytes written or DMAed from the ...
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Bit 5-3: Reflect the IRQ resource assigned for ECP port. cnfgB[5:3] 000 reflect other IRQ resources selected by PnP register (default) 001 IRQ7 010 IRQ9 011 IRQ10 100 IRQ11 101 IRQ14 110 IRQ15 111 IRQ5 Bit 2-0: These five bits ...
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Configuration Mode. The confgA and confgB registers are accessible at 0x400 and 0x401 in this mode. Bit 4: Read/Write (Valid only in ECP Mode) 1 Disables the interrupt generated on the asserting edge of nFault. 0 Enables an interrupt ...
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ECP Pin Descriptions NAME TYPE nStrobe (HostClk) PD<7:0> I/O nAck (PeriphClk) Busy (PeriphAck) PError (nAckReverse) Select (Xflag) nAutoFd (HostAck) nFault (nPeriphRequest) nInit (nReverseRequest) nSelectIn (ECPMode) DESCRIPTION O The nStrobe registers data or address into the slave on the asserting ...
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ECP Operation The host must negotiate on the parallel port to determine if the peripheral supports the ECP protocol before ECP operation. After negotiation necessary to initialize some of the port bits. The following are required: (a) ...
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DMA Transfers DMA transfers are always to or from the ecpDFifo, tFifo, or CFifo. The DMA uses the standard PC DMA services. The ECP requests DMA transfers from the host by activating the PDRQ pin. The DMA will empty ...
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KEYBOARD CONTROLLER The KBC (8042 with licensed KB BIOS) circuit of W83977EF/CTF is designed to provide the functions needed to interface a CPU with a keyboard and/or a PS/2 mouse, and can be used with IBM - compatible personal ...
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Status Register The status register is an 8-bit read-only register at I/O address 64H (Default, PnP programmable I/O address LD5-CR62 and LD5-CR63), that holds information about the status of the keyboard controller and interface. It may be read at ...
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Commands COMMAND 20h Read Command Byte of Keyboard Controller 60h Write Command Byte of Keyboard Controller A4h Test Password Returns 0Fah if Password is loaded Returns 0F1h if Password is not loaded A5h Load Password Load Password until a ...
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Commands, continued COMMAND ABh Interface Test ADh Disable Keyboard Interface AEh Enable Keyboard Interface C0h Read Input Port(P1) and send data to the system C1h Continuously puts the lower four bits of Port1 into STATUS register C2h Continuously puts ...
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KB Control Register (Logic Device 5, CR-F0) BIT 7 6 NAME KCLKS1 KCLKS0 Reserved Reserved Reserved KCLKS1, KCLKS0 This 2 bits are for the KBC clock rate selection KBC clock input is 6 Mhz = 0 ...
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OnNow / Security Keyboard and Mouse Wake-Up ---- Programmable Keyboard / Mouse Wake-Up Functions Winbond's unique programmable keyboard/ mouse Wake-Up functions provide the system with diversified methods for either OnNow Wake-Up application, or security control application. The keyboard or ...
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GENERAL PURPOSE I/O W83977EF/CTF provides 14 Input/Output ports that can be individually configured to perform a simple basic I/O function or a pre-defined alternate function. These 14 GP I/O ports are divided into three groups, the first group contains ...
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W83977EF/ CTF Figure 7.2 Figure 7.3 Publication Release Date: March 1999 -85 - PRELIMINARY Revision A1 ...
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Basic I/O functions The Basic I/O functions of W83977EF/CTF provide several I/O operations including driving a logic value to output port, latching a logic value from input port, inverting the input/output logic value, and steering Common Interrupt (only available ...
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Table 7.1.2 GP I/O PORT ACCESSED REGISTER GP1 GP2 REGISTER BIT GP I/O PORT ASSIGNMENT BIT 0 GP10 BIT 1 GP11 BIT 2 GP12 BIT 3 GP13 BIT 4 GP14 BIT 5 GP15 BIT 6 GP16 BIT 7 GP17 BIT ...
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Alternate I/O Functions W83977EF/CTF provides several alternate functions which are divided among the GP I/O ports. Table 7.2.1 shows their assignments. Polarity bit can also be set to alter their polarity. Table 7.2.1 GP I/O PORT GP10 Interrupt Steering ...
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Watch Dog Timer Output Watch Dog Timer contains a one second/minute resolution down counter, CRF2 of Logical Device 8, and two Watch-Dog control registers, WDT_CTRL0 and WDT_CTRL1 of Logical Device 8. The down counter can be programmed within the ...
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... FDC (logical device 0), PRT (logical device 1), UART1 (logical device 2), UART2 (logical device 3), KBC (logical device 5), CIR (logical device 6)(For W83977CTF only), GPIO1 (logical device 7), GPIO2 (logical device 8), and ACPI ((logical device A). Each Logical Device has its own configuration registers (above CR30). Host can access these registers by writing an appropriate logical device number into logical device select register at CR7 ...
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After Power-on reset, the value on RTSA (pin 43) is latched by HEFRAS of CR26. In Compatible PnP, a specific value (87h) must be written twice to the Extended Functions Enable Register (I/O port address 3F0h or 370h). Secondly, an ...
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Configurate the configuration registers The chip selects the logical device and activates the desired logical devices through Extended Function Index Register (EFIR) and Extended Function Data Register (EFDR). EFIR is located at the same address as EFER, and EFDR ...
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ACPI REGISTERS FEATURES W83977EF/CTF supports both ACPI and legacy power managements. The switch logic of the power management block generates an SMI# interrupt in the legacy mode and an SCI# interrupt in the ACPI mode. The new ACPI feature ...
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... Bit LDNB7 - LDNB0 --> Logical Device Number Bit CR20 Bit DEVIDB7 - DEBIDB0 --> Device ID Bit 7 - Bit 0 = 0x52 (read only). CR21 Bit DEVREVB7 - DEBREVB0 --> Device Rev Bit 7- Bit 0 = 0x7x (read only for W83977CTF). 0xFx (read only for W83977EF). CR22 (Default 0xff) Bit Reserved. Bit 5: URBPWD ...
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CR24 (Default 0b1s000s0s) Bit 7: EN16SA = 0 12 bit Address Qualification = 1 16 bit Address Qualification Bit 6: EN48 = 0 The clock input on Pin 1 should be 24 Mhz The clock input on Pin ...
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CR26 (Default 0b0s000000) Bit 7: SEL4FDD = 0 Select two FDD mode Select four FDD mode. Bit 6: HEFRAS These two bits define how to enable Configuration mode. The corresponding power-on setting pin is NRTSA (pin 43). HEFRAS ...
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CR28 (Default 0x00) Bit Reserved. Bit 4: IRQ Sharing selection Disable IRQ Sharing = 1 Enable IRQ Sharing Bit 3:Reserved Bit PRTMODS2 - PRTMODS0 = 0xx Parallel Port Mode = 100 Reserved ...
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CR2B (Default 0x00) Bit PIN73S1, PIN73S0 = 00 PANSWIN GP23 = 10 Reserved = 11 Reserved Bit 5: PIN72S = 0 PANSWOUT GP22 Bit PIN70S1, PIN70S0 = 00 SMI# = ...
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IRQ15 = 01 GP15 = 10 WDTO = 11 Reserved Bit PIN103S1, PIN103S0 = 00 IRQ14 = 01 GP14 = 10 PLEDO = 11 Reserved CR2D (Default 0x00) Test Modes: Reserved for Winbond. CR2E (Default ...
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Logical Device 0 (FDC) CR30 (Default 0x01 if PNPCSV during POR, default 0x00 otherwise) Bit Reserved. Bit Activates the logical device Logical device is inactive. CR60 (Default ...
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Bit Interface Mode = 11 AT Mode (Default (Reserved PS Model 30 Bit 1: FDC DMA Mode = 0 Burst Mode is enabled = 1 Non-Burst Mode (Default) Bit 0: Floppy ...
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CRF2 (Default 0xFF) Bit FDD D Drive Type Bit FDD C Drive Type Bit FDD B Drive Type Bit 1:0: FDD A Drive Type When FDD is in enhanced 3-mode(CRF0.bit0=1), these ...
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CRF5 (Default 0x00) FDD1 Selection: Same as FDD0 of CRF4. TABLE A Drive Rate Table Select DRTS1 DRTS0 DRATE1 Note:Refer to CRF2 for SELDEN value in the cases when CRF0, bit0=1. TABLE B DMOD0 ...
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Logical Device 1 (Parallel Port) CR30 (Default 0x01 if PNPCSV during POR, default 0x00 otherwise) Bit Reserved. Bit Activates the logical device Logical device is inactive. CR60 ...
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Logical Device 2 (UART A) ¢) 10.4 CR30 (Default 0x01 if PNPCSV during POR, default 0x00 otherwise) Bit Reserved. Bit Activates the logical device Logical device is inactive. CR60, CR ...
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CRF0 (Default 0x00) Bit Reserved. Bit 3: RXW4C = 0 No reception delay when SIR is changed from TX mode to RX mode Reception delays 4 characters-time (40 bit-time) when SIR is changed from TX ...
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Bit 2: HDUPLX. IR half/full duplex function select The IR function is Full Duplex The IR function is Half Duplex. Bit 1: TX2INV the SOUTB pin of UART B function or IRTX pin of ...
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Logical Device 5 (KBC) CR30 (Default 0x01 if PENKBC= 1 during POR, default 0x00 otherwise) Bit Reserved. Bit Activates the logical device Logical device is inactive. CR60 (Default 0x00, ...
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Logical Device 6 (CIR) CR30 (Default 0x00) Bit Reserved. Bit Activates the logical device Logical device is inactive. CR60 (Default 0x00) These two registers select CIR I/O base address ...
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CRE0 (GP10, Default 0x01) Bit Reserved. Bit 4: IRQ Filter Select = 1 Debounce Filter Enabled = 0 Debounce Filter Bypassed Bit 3: Select Function Select Alternate Function: Interrupt Steering Select Basic I/O ...
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CRE2 (GP12, Default 0x01) Bit Reserved. Bit Select Function Select Basic I/O function Select 1st alternate function: Watch Dog Timer Output Reserved = 11 Reserved Bit 2: Reserved. ...
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CRE5 (GP15, Default 0x01) Bit Address decoder is 1-Byte boundary Address decoder is 2-Byte boundary Address decoder is 4-Byte boundary Address decoder is 8-Byte boundary. Bit 5: Reserved. Bit ...
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TABLE C WDT_CTRL1* BIT[1]* WDT_CTRL0* BIT[ *Note: 1). Regarding to the contents of WDT_CTR1 and WDT_CTRL0, please refer to CRF3 and CRF4 in Logic Device 8. 2). Continuous high or low depends on the polarity bit ...
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CRE8 (GP20, Default 0x01) Bit Reserved. Bit Select Function Select basic I/O function = 01 Reserved = 10 Select alternate function: Keyboard Reset (connected to KBC P20 Reserved Bit 2: ...
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Reserved = 10 Select 2nd alternate function: Keyboard P15 I Reserved Bit 2: Int Enable Common IRQ = 0 Disable Common IRQ Bit 1: Polarity: 1: Invert Invert Bit 0: In/Out: ...
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CRF0 (Default 0x00) Debounce Filter Enable or Disable for General Purpose I/O Combined Interrupt. The Debounce Filter can reject a pulse with 1ms width or less. Bit Reserved Bit 3: GP Common IRQ Filter Select = 1 ...
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Bit 2: Mouse interrupt reset Enable or Disable = 1 Watch Dog Timer is reset upon a Mouse interrupt = 0 Watch Dog Timer is not affected by Mouse interrupt Bit 1: Keyboard interrupt reset Enable or Disable = 1 ...
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... Bit 0: KBXKEY. Enable any character received from Keyboard to Wake-Up the system Only predetermined specific key combination can Wake-Up the system Any character received from Keyboard can Wake-Up the system. W83977EF/ CTF Publication Release Date: March 1999 -118 - PRELIMINARY . (for W83977CTF only) Revision A1 ...
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CRE1 (Default 0x00) Keyboard Wake-Up Index Register This register is used to indicate which Keyboard Wake-Up Shift register or Predetermined key Register read/written via CRE2. The range of Keyboard Wake-Up index register is 0x00 - 0x0E, and ...
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Bit 2: Enable all wake-up event set in CRE0 can wake-up the system from S1/S2 state. This bit is cleared when wake-up event occurs Disable Enable. Bit Reserved. CRE5 (Default 0x00) Bit 7: ...
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Bit 2: FDCPME. FDC auto power management enable disable the auto power management functions enable the auto power management functions. Bit 1: URAPME. UART A auto power management enable disable the auto power management ...
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Bit 2: FDCTRAPSTS. FDC trap status FDC is now in the sleeping state FDC is now in the working state due to any FDC access, any IRQ, any DMA acknowledge, or any enabling of the motor ...
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CRF6 (Default 0x00) Bit 7: Reserved. Return zero when read. Bit Enable bits of the SMI#/SCI# generation due to the device's IRQ. These bits enable the generation of an SMI#/SCI# interrupt due to any IRQ of the ...
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Bit 2: COMIRQEN disable the generation of an SMI#/SCI# interrupt due to common IRQ function's IRQ enable the generation of an SMI#/SCI# interrupt due to common IRQ function's IRQ. Bit 1: GP11IRQEN disable the ...
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SPECIFICATIONS 11.1 Absolute Maximum Ratings PARAMETER Power Supply Voltage Input Voltage Battery Voltage V BAT 5V Standby V SB Operating Temperature Storage Temperature Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life ...
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DC CHARACTERISTICS, continued PARAMETER SYM. I/O - CMOS level bi-directional pin with source-sink capability Input Low Voltage V IL Input High Voltage V IH Output Low Voltage V OL Output High Voltage V OH Input ...
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DC CHARACTERISTICS, continued PARAMETER SYM. I/O - TTL level bi-directional pin with source-sink capability 12t Input Low Voltage V IL Input High Voltage V IH Output Low Voltage V OL Output High Voltage V OH Input ...
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DC CHARACTERISTICS, continued PARAMETER IN - CMOS level input pin c Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage IN - CMOS level Schmitt-triggered input pin cs Input Low Threshold Voltage Input High Threshold Voltage ...
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AC Characteristics 11.3.1 FDC: Data rate = 1 MB, 500 KB, 300 KB, 250 KB/sec. PARAMETER SA9-SA0, AEN, DACK#, CS#, setup time to IOR# ¡õ SA9-SA0, AEN, DACK#, hold time for IOR# ¡ô IOR width Data access time from ...
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AC Characteristics, FDC continued PARAMETER IOW# or IOR# response time from DRQ TC width RESET width INDEX# width DIR# setup time to STEP# DIR# hold time from STEP# STEP# pulse width STEP# cycle width WD# pulse width Write precompensation ...
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UART/Parallel Port PARAMETER Delay from Stop to Set Interrupt Delay from IOR# Reset Interrupt Delay from Initial IRQ Reset to Transmit Start Delay from IOW# to Reset interrupt Delay from Initial IOW# to interrupt Delay from Stop to Set ...
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EPP Data or Address Read Cycle Timing Parameters PARAMETER Ax Valid to IOR# Asserted IOCHRDY Deasserted to IOR# Deasserted IOR# Deasserted to Ax Valid IOR# Deasserted to IOW# or IOR# Asserted IOR# Asserted to IOCHRDY Asserted PD Valid to ...
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EPP Data or Address Write Cycle Timing Parameters PARAMETER Ax Valid to IOW# Asserted SD Valid to Asserted IOW# Deasserted to Ax Invalid WAIT# Deasserted to IOCHRDY Deasserted Command Asserted to WAIT# Deasserted IOW# Deasserted to IOW# or IOR# ...
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Parallel Port FIFO Timing Parameters PARAMETER DATA Valid to nSTROBE Active nSTROBE Active Pulse Width DATA Hold from nSTROBE Inactive BUSY Inactive to PD Inactive BUSY Inactive to nSTROBE Active nSTROBE Active to BUSY Active 11.3.7 ECP Parallel Port ...
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KBC Timing Parameters NO. T1 Address Setup Time from WRB T2 Address Setup Time from RDB T3 WRB Strobe Width T4 RDB Strobe Width T5 Address Hold Time from WRB T6 Address Hold Time from RDB T7 Data Setup ...
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GPIO Timing Parameters SYMBOL t Write data to GPIO update WGO Note : Refer to Microprocessor Interface Timing for Read Timing. 11.3.11 Keyboard/Mouse Timing Parameters SYMBOL t PANSWIN# falling edge to PANSWOUT# falling edge SWL t PANSWIN# falling edge ...
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TIMING WAVEFORMS 12.1 FDC Processor Read Operation SA0-SA9 AEN CS# TAR DACK# IOR# TFD D0-D7 IRQ Processor Write Operation SA0-SA9 AEN TAW DACK# IOW# D0-D7 IRQ DMA Operation TAM DRQ DACK# TMA IOW# or IOR# TMW (IOW#) TMR (IOR#) ...
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UART/Parallel SIN (RECEIVER INPUT DATA) IRQ3 or IRQ4 IOR (READ RECEIVER BUFFER REGISTER) SERIAL OUT (SOUT) THRS IRQ3 or IRQ4 THR IOW (WRITE THR) IOR (READ TIR) Receiver Timing STAR DATA BITS (5-8) PARITY Transmitter Timing STAR DATA (5-8) ...
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Modem Control Timing IOW# (WRITE MCR) RTS#,DTR# ¢x CTS#,DSR# ¢x DCD# ¢x ¡÷ ¢x IRQ3 or IRQ4 IOR# (READ MSR) RI# ACK# IRQ7 MODEM Control Timing ¢x ¢x ¢x ¡÷ ¡ö ¢x TMWO ¢x ¢x ¢x ¢x ¢ ¢x ...
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Parallel Port 12.3.1 Parallel Port Timing IOW# INIT#, STROBE# AUTOFD, SLCTIN# PD<0:7> ACK# IRQ (SPP) IRQ (EPP or ECP) nFAULT (ECP) ERROR# (ECP) IRQ Publication Release Date: March 1999 -140 - W83977EF/ CTF PRELIMINARY ...
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EPP Data or Address Read Cycle (EPP Version 1.9) A<0:10> t1 IOR SD<0:7> t5 IOCHRDY t10 t13 t14 WRITE# t16 PD<0:7> t22 t23 t24 ADDRSTB DATASTB WAIT t18 t17 t21 t25 t27 t26 -141 - ...
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EPP Data or Address Write Cycle (EPP Version 1.9) A10-A0 SD<0:7> t1 IOW# IOCHRDY WRITE# PD<0:7> DATAST# ADDRSTB# WAIT# t22 PBDIR t10 t11 t13 t15 t16 t17 t19 t20 -142 - W83977EF/ CTF PRELIMINARY t3 ...
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EPP Data or Address Read Cycle (EPP Version 1.7) A<0:10> t1 IOR SD<0:7> t5 IOCHRDY t10 t13 t14 WRITE# t16 PD<0:7> t22 t23 ADDRSTB t24 DATASTB WAIT t18 t17 t21 t26 t27 -143 - W83977EF/ ...
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EPP Data or Address Write Cycle (EPP Version 1.7) A10-A0 SD<0:7> t1 IOW# IOCHRDY WRITE# PD<0:7> DATAST# ADDRSTB# WAIT# 12.3.6 Parallel Port FIFO Timing PD<0:7> nSTROBE BUSY t10 t11 t13 t15 t16 t17 t19 t20 ...
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ECP Parallel Port Forward Timing nAUTOFD PD<0:7> nSTROBE BUSY 12.3.8 ECP Parallel Port Reverse Timing PD<0:7> nACK nAUTOFD -145 - W83977EF/ CTF PRELIMINARY ...
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KBC 12.4.1 Write Cycle Timing A2, CSB WRB D0~D7 GA20 OUTPUT PORT FAST RESET PULSE RC FE COMMAND 12.4.2 Read Cycle Timing A2,CSB AEN RDB D0-D7 12.4.3 Send Data to K/B CLOCK (KCLK) T12 SERIAL DATA START (KDAT) T1 ...
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Receive Data from K/B CLOCK (KCLK) T15 SERIAL DATA START (T1) T20 12.4.5 Input Clock CLOCK CLOCK T21 12.4.6 Send Data to Mouse MCLK T25 MDAT START Bit 12.4.7 Receive Data from Mouse MCLK T29 MDAT START T14 T13 ...
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GPIO Write Timing Diagram A0-A15 IOW# D0-7 GPIO10-17 GPIO20-25 12.6 Master Reset (MR) Timing Vcc MR 12.7 Keyboard/Mouse Wake-up Timing KCLK MCLK PANSWIN# PANSWOUT# HI-Z tSWL VALID VALID PREVIOUS STATE tVMR tWKUPD tSWZ -148 - W83977EF/ CTF PRELIMINARY VALID ...
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APPLICATION CIRCUITS 13.1 Parallel Port Extension FDD 13 WE2#/SLCT 25 12 WD2#/ MOB2#/BUSY 23 10 DSB2#/ACK 22 9 PD7 21 8 PD6 20 7 PD5 19 6 DCH2#/PD4 18 RDD2#/PD3 5 17 STEP2#/SLIN# 4 WP2#/PD2 16 DIR2#/INIT# ...
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Parallel Port Extension 2FDD 13 WE2#/SLCT 25 12 WD2#/PE 24 MOB2#/BUSY DSB2#/ACK 22 9 DSA2#/PD7 21 8 MOA2#/PD6 20 7 PD5 19 6 DCH2#/PD4 18 RDD2#/PD3 5 STEP2#/SLIN WP2#/PD2 16 DIR2#/INIT# 3 TRK02#/PD1# 15 ...
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... MOB# 14.0 ORDERING INFORMATION PART NO. KBC FIRMWARE W83977EF-PW Phoenix MultiKey/42 W83977EF-AW AMIKEY W83977CTF-PW Phoenix MultiKey/42 W83977CTF-AW AMIKEY 15.0 HOW TO READ THE TOP MARKING Example: The top marking of W83977EF-AW inbond W83977EF-AW AM. MEGA. 87-96 821A2B282012345 1st line: Winbond logo 2nd line: the type number: W83977EF-AW 3rd line: the source of KBC F/W -- American Megatrends Incorporated ...
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PACKAGE DIMENSIONS (128-pin PQFP 102 103 128 See Detail F y Seating Plane Headquarters No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5792646 http://www.winbond.com.tw/ Voice & ...