W233 Cypress Semiconductor Corp., W233 Datasheet

no-image

W233

Manufacturer Part Number
W233
Description
Spread Spectrum FTG For Via Mobile K7 Chipset
Manufacturer
Cypress Semiconductor Corp.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
W233H
Manufacturer:
CY
Quantity:
240
Company:
Part Number:
W233H
Quantity:
100
Cypress Semiconductor Corporation
Document #: 38-07250 Rev. **
Features
Key Specifications
CPU to CPU Output Skew: ......................................... 175 ps
PCI to PCI Output Skew: ............................................ 500 ps
V
SDRAMIN to SDRAM0:5 Delay: ............................2.0 ns typ.
• Maximized EMI Suppression using Cypress’s Spread
• Single-chip system frequency synthesizer for VIA Mo-
• Two copies of CPU output
• Seven copies of PCI output
• One 48-MHz output for USB
• One 24-MHz or 48-MHz output for SIO
• Three buffered reference outputs
• Six SDRAM outputs provide support for three SODIMMs
• Supports frequencies up to 166 MHz
• SMBus interface for programming
• Power management control inputs
• Available in 48-pin SSOP
Block Diagram
DD
SDRAM_STOP#
Spectrum technology
bile K7 chipset
PCI_STOP#
CLK_STOP#
CPU_STOP#
: ........................................................................ 3.3V±5%
SDRAMIN
SDATA
SCLK
X1
X2
SMBus
PLL 1
Logic
PLL2
XTAL
OSC
÷2,3,4
Control
Clock
Control
Stop
Clock
I/O Pin
Control
Control
Stop
Clock
Stop
Spread Spectrum FTG for VIA Mobile K7 Chipset
Control
Clock
Stop
÷2
7
REF2/FS3*
VDD_CPU
VDD_48MHz
48MHz/FS0
VDD_REF
REF0_2X
REF1
VDD_PCI
CPU_CS
PCI_F/FS2
PCI0/FS1
PCI1
PCI2
PCI3
PCI4
PCI5
CPUT0_F
CPUC0_F
PCI6
*SEL24_48#/24_48MHz
VDD_SDRAM
SDRAM0:5
SDRAM_F
3901 North First Street
PRELIMINARY
Table 1. Pin Selectable Frequency
*SEL24_48#/24_48MHz
FS3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
Note:
Pin Configuration
1.
*SDRAM_STOP#
Internal pull-up resistors should not be relied upon for setting I/O
pins HIGH.
Input Address
FS2
GND_48MHz
*PCI_STOP#
VDD_48MHz
GND_CORE
*FS0/48MHz
San Jose
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
VDD_CORE
*FS2/PCI_F
VDD_REF
*FS1/PCI0
SDRAMIN
GND_PCI
GND_PCI
VDD_PCI
VDD_PCI
PCI1
PCI2
PCI3
PCI4
PCI5
PCI6
FS1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
X1
X2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
FS0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
[1]
CA 95134
Revised September 27, 2001
133.3
100.0
133.3
100.0
133.3
100.0
133.3
100.0
102.0
104.0
106.0
108.0
110.0
111.0
112.0
(MHz)
95.0
CPU
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF0_2X
REF1
REF2/FS3*
GND_REF
GND_CPU
VDD_CPU
CPU_CS
CPUT0_F
CPUC0_F
CPU_STOP#*
STOP_CLK#*
SDRAM0
SDRAM1
VDD_SDRAM
GND_SDRAM
SDRAM2
SDRAM3
GND_SDRAM
VDD_SDRAM
SDRAM4
SDRAM5
SDRAM_F
SCLK
SDATA
(MHz)
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
31.7
34.0
34.6
35.3
36.0
36.6
37.0
37.3
PCI
408-943-2600
W233
±0.25%
±0.25%
Spectrum
±0.5%
±0.5%
–0.5%
–0.5%
Spread
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF

Related parts for W233

W233 Summary of contents

Page 1

... SDRAM3 SDRAMIN 18 31 GND_SDRAM 19 30 VDD_SDRAM 29 SDRAM4 SDRAM5 22 27 SDRAM_F 26 SCLK SDATA • CA 95134 • 408-943-2600 Revised September 27, 2001 W233 Spread Spectrum OFF OFF ±0.5% ±0.5% –0.5% –0.5% ±0.25% ±0.25% OFF OFF OFF OFF OFF OFF OFF OFF ...

Page 2

... STOP_CLK# Input: LVTTL-compatible input that places the device in stop- clock mode when held LOW. In stop-clock mode, CPUT0_F and CPUC0_F will be active and all the other output clocks will be driven LOW. STOP_CLK asynchronous input. W233 will not complete the current clock cycle when STOP_CLK# is being driven LOW. I/O 48-MHz Output/Frequency Select 0: 48 MHz is provided in normal operation ...

Page 3

... CPUT0_F and CPUC0_F. P Power Connection: Power supply for core logic, PLL circuitry, SDRAM out- puts, PCI outputs, reference outputs, 48-MHz output, and 24_48-MHz output. Connect to 3.3V supply G Ground Connections: Connect all ground pins to the common system ground plane. Pin Description Page W233 ...

Page 4

... Figure 2. Input Logic Selection Through Jumper Option Document #: 38-07250 Rev. ** PRELIMINARY Upon W233 power-up, the first operation is used for input logic selection. During this period, the five I/O pins (4, 5, 22, 23, 46) are three-stated, allowing the output strapping re- sistor on the l/O pins to pull the pins and their associated ca- pacitive clock load to either a logic HIGH or LOW state. At the end of the 2-ms period, the established logic “ ...

Page 5

... Spread Spectrum clocking is activated or deactivated by se- lecting the appropriate data bytes of the SMBus data stream. Refer to Table 5 for more details. Typical Clock Spread Spectrum Enabled Figure 4. Typical Modulation Profile W233 EMI Reduction Non- Spread Speactrum Frequency Span (MHz) Down Spread Page ...

Page 6

... Refer to Table 4 The data bits in Data Bytes 0–7 set internal W233 registers that control device operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted above. For description of bit control functions, refer to Table 4, Data Byte Serial Configuration Map ...

Page 7

... Active Low Active Low Active Low Active Low Active Low Active Low Active -- -- 24-MHz 48-MHz Low Active Low Active Low Active Low Active Low Active Page W233 Default ...

Page 8

... Bit Control 0 1 Low Active -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Low Active Low Active Low Active -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Page W233 Default ...

Page 9

... W233 Output Frequency PCI Spread Spectrum 33.3 OFF 33.3 OFF 33.3 ±0.5% 33.3 ±0.5% 33.3 –0.5% 33.3 –0.5% 33.3 ±0.25% 33.3 ±0.25% 31.7 OFF 34.0 OFF 34.6 OFF 35.3 OFF 36.0 OFF 36.6 OFF 37 ...

Page 10

... All clock outputs loaded with 6" 60 transmission lines with 20-pF capacitors. 3. W233 logic inputs (except FS3) have internal pull-up devices (pull-ups not full CMOS level). Logic input FS3 has an internal pull-down device. Document #: 38-07250 Rev. ** PRELIMINARY above those specified in the operating sections of this specifi- cation is not implied ...

Page 11

... X1 input threshold voltage (typical The W233 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF; this includes typical stray capacitance of short PCB traces to crystal input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). ...

Page 12

... Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to fre- quency stabilization. Average value during switching transition. Used for determining series termination value. W233 Min. Typ. Max. Unit ...

Page 13

... Length = 5” Figure 5. K7 Open Drain Clock Driver Test Circuit Package Type 48-pin SSOP (300 mils) Min. Typ. Max. 24.004 +167 57/34 0 Length = 3 ” T2 20p 1. Length = 3 ” T5 20p Page W233 Unit MHz ppm 2 V/ ...

Page 14

... & 10– 0.005 F V =VIA to respective supply plane layer by passes = 0 0.1 F W233 Page ...

Page 15

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY W233 Page ...

Page 16

... Document Title: W233 Spread Spectrum FTG for VIA Mobile K7 Chipset Document Number: 38-07250 Issue REV. ECN NO. Date ** 110515 01/07/02 Document #: 38-07250 Rev. ** PRELIMINARY Orig. of Change SZV Change from Spec number: 38-01037 to 38-07250 Description of Change Page W233 ...

Related keywords