ssm2517 Analog Devices, Inc., ssm2517 Datasheet
ssm2517
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ssm2517 Summary of contents
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... GSM interference or other digital signals on the transmitted audio. The SSM2517 is capable of delivering 2 continuous output power with <1% THD + N driving a 4 Ω load from a 5.0 V supply. The SSM2517 features a high efficiency, low noise modulation scheme that requires no external LC output filters ...
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... SSM2517 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Digital Input Specifications ......................................................... 4 PDM Interface Digital Timing Specifications .......................... 5 Absolute Maximum Ratings ............................................................ 6 Thermal Resistance ...................................................................... 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 8 Theory of Operation ...................................................................... 13 REVISION HISTORY 5/11—Rev Rev. A Changes to Table 6, LRSEL Pin Description ................................. 7 10/10— ...
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... S PVDD = 5 Dither input, 8 Ω µH load VDD VDD = 3 64× S VDD = 3 128× S VDD = 1 64× S VDD = 1 128× S Rev Page SSM2517 = 128×, PDM clock = 6.144 MHz; S Min Typ Max Unit 2.4 W 1.38 W 1.2 W 0.7 W 1.5 W 0.9 W 0.035 % 0 ...
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... SSM2517 Parameter Standby Current Shutdown Current NOISE PERFORMANCE Output Voltage Noise Signal-to-Noise Ratio DIGITAL INPUT SPECIFICATIONS Table 2. Parameter INPUT SPECIFICATIONS Input Voltage High PCLK, PDAT, LRSEL Pins GAIN_FS Pin Input Voltage Low PCLK, PDAT, LRSEL Pins GAIN_FS Pin Input Leakage High ...
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... DE The SSM2517 was designed so that the data line can transition coincident with or close to a clock edge not necessary to delay the data line transition until after the 1 clock edge because the SSM2517 does this internally to ensure good timing margins. The data line should remain constant during the valid sample period illustrated in Figure 2 ...
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... SSM2517 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings apply at 25°C, unless otherwise noted. Table 4. Parameter PVDD Supply Voltage VDD Supply Voltage Input Voltage (Signal Source) ESD Susceptibility OUT− and OUT+ Pins Storage Temperature Range Operating Temperature Range Junction Temperature Range ...
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... Amplifier Power, 2 5.5 V. Amplifier Ground. Inverting Output. Left/Right Channel Select. Pull up to VDD for right channel; tie to ground for left channel. Digital Power, 1. 3.6 V. PDM Interface Master Clock. PDM Data Signal. Gain and Sample Rate Selection Pin. Rev Page SSM2517 ...
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... SSM2517 TYPICAL PERFORMANCE CHARACTERISTICS 100 = 8Ω + 33µ GAIN = 5V SAMPLE RATE = 64× (3.072MHz PVDD = 2.5V 0.1 0.01 0.001 0.01 0.1 OUTPUT POWER (W) Figure 4. THD + N vs. Output Power into 8 Ω, Gain = 100 = 8Ω + 33µ GAIN = 3.6V SAMPLE RATE = 64× (3.072MHz PVDD = 2.5V 0.1 0.01 0.001 0.01 0.1 OUTPUT POWER (W) Figure 5. THD + N vs. Output Power into 8 Ω ...
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... Figure 14. THD + N vs. Frequency, PVDD = 5 V, Gain = 5 V, 100 10 1 0.1 0.01 10k 100k 10 Figure 15. THD + N vs. Frequency, PVDD = 3.6 V, Gain = 3.6 V, Rev Page SSM2517 = 4Ω + 15µ GAIN = 3.6V SAMPLE RATE = 128× (6.144MHz) PVDD = 3.6V PVDD = 2.5V PVDD = 5V 0.01 0.1 1 OUTPUT POWER (W) = 4Ω + 15µH ...
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... SSM2517 100 = 8Ω + 33µ PVDD = 2.5V GAIN = 3.6V SAMPLE RATE = 64× 10 (3.072MHz) 1 0.2W 0.1W 0.1 0.05W 0.01 10 100 1k FREQUENCY (Hz) Figure 16. THD + N vs. Frequency, PVDD = 2.5 V, Gain = 3 Ω 64× 4.0 GAIN = 5V = 4Ω + 15µH SAMPLE RATE = 64× (3.072MHz) 3.5 = 8Ω + 33µ 3.0 NO LOAD 2.5 2.0 1.5 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) Figure 17. Quiescent Current (H-Bridge) vs. Supply Voltage, Gain = 64× ...
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... SAMPLE RATE = 64× (3.072MHz) 600 500 400 PVDD = 2.5V 300 200 100 0 1.6 1.8 2.0 0 Figure 27. Supply Current (H-Bridge) vs. Output Power into 4 Ω, Rev Page SSM2517 = 4Ω + 15µ GAIN = 5V SAMPLE RATE = 128× (6.144MHz) THD + N = 10% THD + 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE ( Ω 128× ...
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... SSM2517 0 –10 –20 –30 –40 –50 –60 PVDD = 3.6V –70 –80 PVDD = 5V –90 –100 10 100 1k FREQUENCY (Hz) Figure 28. Power Supply Rejection Ratio (PSRR) vs. Frequency –1 –2 –40 10k 100k Rev Page OUTPUT PCLK – 100 120 140 TIME (µ ...
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... PDM stop condition of at least 128 repeated 0xAC bytes (1024 clock cycles), it places the SSM2517 in the standby state. In the standby state, the PCLK can be removed, resulting in a full power-down state. This state is the lowest power condition possible. When the PCLK is turned ...
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... SSM2517 PDM PATTERN CONTROL The SSM2517 has a simple control mechanism that can set the part for low power states and control functionality. This is accomplished by sending a repeating 8-bit pattern to the device. Different patterns set different functionality (see Table 8). Any pattern must be repeated a minimum of 128 times. The ...
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... PVDD pin and 0.1 µF for the VDD pin. This capacitor bypasses low frequency noises to the ground plane. For high frequency transient noises, use a 0.1 µF capacitor as close as possible to the PVDD and VDD pins of the device. Placing the decoupling capacitors as close as possible to the SSM2517 helps to maintain efficient performance. Rev Page SSM2517 ...
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... ORDERING GUIDE Model 1 Temperature Range SSM2517CBZ-R7 −40°C to +85°C SSM2517CBZ-RL −40°C to +85°C EVAL-SSM2517Z RoHS Compliant Part. ©2010-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 0.655 0.600 0.545 SEATING PLANE 0 ...