pef2045 Infineon Technologies Corporation, pef2045 Datasheet
pef2045
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pef2045 Summary of contents
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Memory Time Switch CMOS (MTSC) Preliminary Data 1 Features Time/space switch for 2048-, 4096- or 8192-kbit/s PCM systems Switching 512 incoming PCM channels 256 outgoing PCM channels 16-input and 8-output PCM lines Different kinds ...
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Pin Configurations (top view) P-LCC-44 Semiconductor Group P-DIP-40 2 PEB 2045 PEF 2045 ...
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Pin Definitions and Functions Pin No. Pin No. Symbol P-LCC P-DIP IN1 7 5 IN5 9 7 IN9 11 9 IN13 13 11 IN14 14 12 IN15 15 13 IN10 ...
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Pin Definitions and Functions (cont’d) Pin No. Pin No. Symbol P-LCC P-DIP DB0 27 25 DB1 29 26 DB2 30 27 DB3 31 28 DB4 32 29 DB5 33 30 DB6 34 31 DB7 35 ...
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Functional Symbol Figure 1 Functional Symbol for the Standard Configuration Figure 2 Functional Symbol for the Primary Access Configuration Semiconductor Group 5 PEB 2045 PEF 2045 ...
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Device Overview The Siemens Memory Time Switch PEx 2045 is a monolithic CMOS circuit connecting any of 512 incoming PCM channels to any of 256 outgoing PCM channels. The on-chip connection memory is accessed via the 8-bit P interface. ...
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PCM IN 2 MHz 16 Figure 4 Memory Time Switch 32/32 for a Non-Blocking 1024-Channel Switch Figure 5 shows the architecture of a primary access board with common channel signaling using four CMOS devices. It exhibits the following functions: ...
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Since the PEx 2045 is a switch for 256 output channels and the SAB 82520 is actually a dual channel controller a quad primary access unit with a non-blocking switch requires a total of 11 devices, – 4 IPAT ® ...
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R IPAT PEB 2235 Line Interface Figure 6 Realization of a Quad Primary Access Interface and Switch with 11 CMOS Devices Semiconductor Group ACFA PEB 2035 HSCC SAB 82520 9 PEB 2045 PEF 2045 MTSC PEB 2045 Synchronous System 2-MHz ...
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Analog SLIC Digital IBC,IEC PCM 2048 kbit/s 1544 kbit/s R IPAT R IPAT Figure 7 Basic Connections to a Digital Switching System Figure 7 shows the PEx 2045 in its different applications in a digital switching system used ...
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Functional Description The PEx 2045 is a memory time switch device. It can connect any of 512 PCM input channels to any of 256 output channels. The input information of a complete frame is stored in the on-chip 4-Kbit ...
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DB7- DB0 A0 P Interface Figure 5 Block Diagram of the PEx 2045 Semiconductor Group MOD STA Connection IAR Memory CM CSR CGR Timing Control SP CLK 12 PEB 2045 PEF 2045 Input Buffer Speech Memory SM Output Buffer ITB00585 ...
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Basic Functional Principles Preparation of the Input Data The PEx 2045 works in 2048-, 4096- or 8192-kbit/s PCM systems. The frame frequency is 8000 Hz in all 3 types of systems. Therefore a frame consists of 32-, 64- or ...
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Figure 9 Latching Instant for Input Data Semiconductor Group 14 PEB 2045 PEF 2045 ...
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As can be seen there the beginning of a input time-slot is defined such, that the input lines have settled to a stable value, when the datum is actually sampled. 4096- and 8192-kbit/s data is sampled in the middle of ...
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Otherwise ( high), an all-zero speech memory address causes the output for the associated channel to be tristate. In this case the all-zero speech memory address (time-slot 0 ...
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Output Buffer The output buffer rearranges the data read from the speech memory. It basically converts the parallel data to serial data. Depending on the tristate control signal from the timing control block the output buffer outputs the data or ...
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Time Slot 127 - 6 7 Time Slot Time Slot bit0 Time Slot 127 - 6 7 Time Slot Time Slot 31 ...
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Microprocessor Interface and Registers The PEx 2045 is programmed via the P interface. It consists of the data bus DB7 … DB0, the address bit A0, the Write (WR), the Read (RD) and Chip Select (CS) signal, as shown ...
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Using the 3 signals A0, WR and RD the IAR, MOD and STA registers can be identified according to table 3. Table 3 Addressing of the Direct Registers The A0 address distinguishes between the IAR and the ...
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It is possible to read or write the direct access registers (i.e. the mode or status register) while an indirect access is in progress. Thus the status register may be read in the time intervals that separate the three sequential ...
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Bits K1 and K0 of the control byte determine whether indirect register access shall be performed. When K1 and K0 are both logical 1, one of the indirect registers is accessed. For all other combinations the ...
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Table 7 Connection Memory Access IA Byte Structure Bit IA7 IA6 IA5 The following example illustrates how an indirect memory access works. The instruction sequence 00110000 01010101 ...
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With the following instruction sequence 00000001 11111111 10101010 the byte sequence 11001110 00000000 10101010 can be ...
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Standard Configuration A logical 1 in the CFS bit of the configuration register sets the PEx 2045 in standard mode (default after power up). All modes from table 9 can be used. The space switch mode (MI1, MI0, MO1, ...
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Figure 14 SYP Duration for The device is synchronized after 3 SP pulses (see chapter 3.2). 2.4 Primary Access Configuration A logical 0 in the CFS bit of the configuration register selects the PEx 2045 for primary ...
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Time-slot 31 of the synchronous 2048-kbit/s interface logical line 2 shall be switched to the system interface logical line 2048-kbit/s system, time-slot 2. The system interface logical output line 1 and the synchronous interface logical input line ...
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According to figure 16 in the primary access configuration the connection memory is usually programmed to switch the system and synchronous interface inputs to the synchronous and system interface outputs, respectively. However also possible to connect the system ...
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The SP signals controls the start of the input and output frame. The output frame starts two before the falling SP edge. However, the rising edge marks the beginning of time-slot 125. Block Select IA7 Block 1 ...
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Operational Description 3.1 Power Up Upon power up the PEx 2045 is set to its initial state. The mode and configuration register bits are all set to logical 1, the clock shift register bits to logical 0. The status ...
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Figure 19 Initializing the PEx 2045 for a 4096-kHz Device Clock 3.3 Operation with a 4096-kHz Device Clock In order for the MTSC to operate with a 4096-kHz device clock the CPS bit in the CFR register needs to be ...
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Standby Mode With MOD:SB being logical 1 the PEx 2045 works as a backup device in redundant systems. It can be accessed via the P interface and works internally like an active device. However, the outputs are high impedance. ...
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Detailed Register Description The following registers may be accessed: Table 8 Addressing the Direct Registers Address The chapters in this section cover the registers in detail. 4.1 Mode Register (MOD) Access: Write on address 0 DB ...
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Table 9 Input/Output Operating Modes MI1 MI0 MO1 ...
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Table 10 Input and Output Pin Arrangement for the Standard Configuration Input Pin Arrangement Pin No Mbit Mbit/s P-LCC P-DIP 4 3 IN1 5 4 IN0 7 5 IN5 8 6 IN4 9 7 IN9 10 ...
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Table 11 Input, Output and Tristate Pin Arrangement for the Primary Access Configuration Pin No. Pin Name P-LCC P-DIP TSC0 5 4 TSC1 8 6 TSC2 10 8 TSC3 12 10 OUT0 43 39 OUT2 41 37 OUT4 38 35 ...
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Status Register (STA) Access: Read at address Busy: The chip is busy resetting the connection memory ( undefined after power up and logical 0 after the device initialization. Note: The ...
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Table 13 Encoding the Different Types of Indirect Accesses Connection Memory Access For a connection memory ...
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The pulse shape factor N may take any integer value from 0 to 255. Space Switch Mode Table 15 Time-Slot and Line Programming for Space Switch Mode Space switch mode 8-Mbit/s input lines 8-Mbit/s output lines N is fixed to ...
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Primary Access Configuration Table 17 Time-Slot and Line Programming for the Primary Access Configuration 2-Mbit/s input lines 4-Mbit/s input lines 8-Mbit/s input lines 2-Mbit/s output lines 4-Mbit/s output lines 8-Mbit/s output lines The interface select bits have to be programmed ...
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Configuration Register Access (CFR) Access: Read or write indirect address FE For a read access the bit 0 of the control byte must be set to logical 1 and for a write access to logical 0. Value after power up ...
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Identical non-zero entries for RS2 – RS0 and XS2 – XS0 as well as identical RRE and XFE generate an output time-slot structure which is 1 time-slot late relative to the input time-slot structure. Identical 000 entries for RS2 – ...
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Electrical Characteristics Absolute Maximum Ratings Parameter Ambient temperature under bias PEB 2045 Storage temperature PEB 2045 Ambient temperature under bias PEF 2045 Storage temperature PEF 2045 Voltage on any pin with respect to ground DC Characteristics Ambient temperature under ...
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AC Characteristics Ambient temperature under bias range, Inputs are driven at 2.4 V for a logical 1 and at 0.4 V for a logical 0. Timing measurements are made at 2.0 V for a logical 1 and at 0.8 V ...
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DB7 Figure 23 P-Read Cycle DB0 - DB7 Figure 24 P-Write Cycle Semiconductor Group t RCY Data Valid t WCY ...
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PCM-Interface Timing Parameter PCM-input setup PCM-input hold PEB 2045 output delay PEF 2045 output delay PEB 2045 tristate delay PEF 2045 tristate delay Clock and Synchronization Timing Parameter Clock period 8 MHz high Clock period 8 MHz low Clock period ...
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CLK Mbit/s OUT 2 Mbit Mbit OUT 4 Mbit/s TS 127 IN 8 Mbit/s Bit 4 TS OUT 8 Mbit/s Bit Example with delayed output frame SP N ...
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CLK Mbit Mbit Mbit 127 Bit 4 8 Mbit/s OUT Time-Slot 2 Mbit/s OUT 2 Mbit/s OUT TS 4 Mbit/s OUT TS 127 Bit 4 8 Mbit/s TSC 2 ...
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Figure 27 PCM-Line Timing in Standard Configuration with a 4-MHz Device Clock Semiconductor Group 49 PEB 2045 PEF 2045 ...
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Figure 28 PCM-Line Timing in Primary Access Configuration with a 4-MHz Device Clock and a CSR Entry (00010001) Semiconductor Group 50 PEB 2045 PEF 2045 ...
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Busy Times Operation Indirect register access Connection memory reset 6 Applications Calculation of Switching Delay for PEB 2045 t 8-MHz Clock Cycle ( = 122 ns) CL Output Line / PCM Mode (Mbit/ OUT 0 OUT 1 OUT ...
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Package Outlines Plastic Package, P-LCC-44 (Plastic Leaded Chip Carrier) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 52 PEB 2045 PEF 2045 Dimensions ...
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Plastic Package, P-DIP-40 (Plastic Dual In-line Package) 2.54 1.5 max 40 1 Index Marking Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 0.25 40x ...