adl5390 Analog Devices, Inc., adl5390 Datasheet

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adl5390

Manufacturer Part Number
adl5390
Description
Rf/if Vector Multiplier
Manufacturer
Analog Devices, Inc.
Datasheet
FEATURES
Matched pair of multiplying VGAs
Broad frequency range 20 MHz to 2.4 GHz
Continuous magnitude control from +5 dB to −30 dB
Output third-order intercept 24 dBm
Output 1 dB compression point 11 dBm
Output noise floor −148 dBm/Hz
Adjustable modulation bandwidth up to 230 MHz
Fast output power disable
Single-supply voltage 4.75 V to 5.25 V
APPLICATIONS
PA linearization and predistortion
Amplitude and phase modulation
Variable matched attenuator and/or phase shifter
Cellular base stations
Radio links
Fixed wireless access
Broadband/CATV
RF/IF analog multiplexer
GENERAL DESCRIPTION
The ADL5390 vector multiplier consists of a matched pair of
broadband variable gain amplifiers whose outputs are summed.
The separate gain controls for each amplifier are linear-in-
magnitude. If the two input RF signals are in quadrature, the
vector multiplier can be configured as a vector modulator or as
a variable attenuator/phase shifter by using the gain control pins
as Cartesian variables. In this case, the output amplitude can be
controlled from a maximum of +5 dB to less than –30 dB, and
the phase can be shifted continuously over the entire 360°
range. Since the signal paths are linear, the original modulation
on the inputs is preserved. If the two signals are independent,
then the vector multiplier can function as a 2:1 multiplexer or
can provide fading from one channel to another.
The ADL5390 operates over a wide frequency range of 20 MHz
to 2400 MHz. For a maximum gain setting on one channel at
380 MHz, the ADL5390 delivers an OP1dB of 11 dBm, an OIP3
of 24 dBm, and an output noise floor of −148 dBm/Hz. The gain
and phase matching between the two VGAs is better than 0.5 dB
and 1°, respectively, over most of the operating range.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
The gain control inputs are dc-coupled with a +/−500 mV dif-
ferential full-scale range centered about a 500 mV common
mode. The maximum modulation bandwidth is 230 MHz,
which can be reduced by adding external capacitors to limit the
noise bandwidth on the control lines.
Both the RF inputs and outputs can be used differentially or
single-ended and must be ac-coupled. The impedance of each
VGA RF input is 250 Ω to ground, and the differential output
impedance is nominally 50 Ω over the operating frequency
range. The DSOP pin allows the output stage to be disabled
quickly to protect subsequent stages from overdrive. The
ADL5390 operates off supply voltages from 4.75 V to 5.25 V
while consuming 135 mA.
The ADL5390 is fabricated on Analog Devices’ proprietary,
high performance 25 GHz SOI complementary bipolar IC
process. It is available in a 24-lead, Pb-free CSP package and
operates over a −40°C to +85°C temperature range. Evaluation
boards are available.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
CMRF
INMQ
INPQ
INMI
INPI
FUNCTIONAL BLOCK DIAGRAM
CMOP
VPRF
RF/IF Vector Multiplier
© 2004 Analog Devices, Inc. All rights reserved.
QBBP
IBBP
Figure 1.
IBBM
OBBM
DSOP
VPS2
ADL5390
www.analog.com
RFOP
RFOM

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adl5390 Summary of contents

Page 1

... The ADL5390 operates over a wide frequency range of 20 MHz to 2400 MHz. For a maximum gain setting on one channel at 380 MHz, the ADL5390 delivers an OP1dB of 11 dBm, an OIP3 of 24 dBm, and an output noise floor of −148 dBm/Hz. The gain and phase matching between the two VGAs is better than 0.5 dB and 1° ...

Page 2

... ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7 General Structure ........................................................................... 11 Theory of Operation .................................................................. 11 Noise and Distortion.................................................................. 11 Applications..................................................................................... 12 Using the ADL5390.................................................................... 12 RF Input and Matching.............................................................. 12 REVISION HISTORY 10/04—Revision 0: Initial Version RF Output and Matching .......................................................... 13 Driving the I-Q Baseband Gain Controls ............................... 13 Interfacing to High Speed DACs.............................................. 14 Generalized Modulator ...

Page 3

... Over any 60 MHz bandwidth At maximum gain setpoint At maximum gain setpoint INPI, INMI, INMQ, INMP (Pins 20, 21, 22, 23) RFOP, RFOM (Pins 9, 10) measured through balun Maximum gain setpoint Over gain setpoint of 0.2 to 1.0 Rev Page ADL5390 Min Typ Max Unit 20 2400 MHz ...

Page 4

... ADL5390 Parameter Output Noise Floor Output IP3 Output 1 dB Compression Point Input 1 dB Compression Point Gain Flatness Gain Matching Phase Matching Input Impedance Output Return Loss F = 900 MHz RF Maximum Gain Gain Conformance Output Noise Floor Output IP3 Output 1 dB Compression Point ...

Page 5

... V tion of this specification is not implied. Exposure to absolute 5.5 V maximum rating conditions for extended periods may affect 10 dBm for 50 Ω device reliability. 2.0 V p-p 825 mW 59°C/W 125°C −40°C to +85°C −65°C to +150°C Rev Page ADL5390 ...

Page 6

... The exposed paddle on the underside of the package should be soldered to a low thermal and electrical Paddle impedance ground plane VPRF 1 18 VPRF QFLP 2 17 IFLP ADL5390 QFLM 3 16 IFLM TOP VIEW QBBP 4 15 IBBP (Not to Scale) QBBM 5 14 IBBM VPS2 6 ...

Page 7

... FREQUENCY (MHz) Gain Setpoint = 1.0 5 σ DASH LINE σ –3 = SOLID LINE 0 –5 – – –20 0 0.25 0.50 0.75 GAIN SETPOINT 900 MHz, 2400 MHz ADL5390 2100 2400 2100 2400 = 70MHz = 140MHz = 380MHz = 900MHz = 2400MHz 1.0 ...

Page 8

... ADL5390 25 σ DASH LINE σ 20 –3 = SOLID LINE –5 –10 –15 –20 0 0.2 0.4 0.6 GAIN SETPOINT Figure 9. Channel-to-Channel Phase Matching vs. Gain Setpoint, RF Frequency = 70 MHz, 140 MHz, 380 MHz, 900 MHz, 2400 MHz 10 σ DASH LINE TEMP = –40°C 8 σ –3 = SOLID LINE TEMP = +25° ...

Page 9

... F = 140MHz 380MHz 900MHz 2400MHz RF 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 GAIN SETPOINT 70 MHz, 140 MHz, 380 MHz, 900 MHz, 2400 MHz F = 70MHz 140MHz 380MHz 900MHz 2400MHz RF 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 GAIN SETPOINT 380 MHz, 900 MHz, 2400 MHz ADL5390 350 400 0.9 1.0 0.9 1.0 ...

Page 10

... SHUNT CAPACITANCE (pF) 200 SHUNT RESISTANCE (Ω) 150 100 50 20 220 420 620 820 1020 1220 1420 1620 1820 2020 2220 F (MHz) RF Figure 21. S11 of RF Input (Shunt R/C Representation) ADL5390 SDD22 90 120 150 → |GRIDZ| 2.7GHz S 11TERMANG I 3GHz 180 10MHz 210 10MHz ...

Page 11

... The broad frequency response of the RF/IF and gain control ports allows the ADL5390 to be used in a variety of applications at different frequencies. The bandwidth for the RF/IF signal path extends from approximately 20 MHz to beyond 2.4 GHz, while the gain controls signals allow for modulation rates greater than 200 MHz ...

Page 12

... VP C4 0.1µF level of the ADL5390 inputs is not affected, as shown in Figure 29. Capacitive reactance at the RF inputs can be compensated for with series inductance. In fact, the customer evaluation board has high impedance line traces between the shunt termi- nation pads and the device input pins, which provides series in- ductance and improves the return loss at 1.9 GHz to better than − ...

Page 13

... DSOP should be tied to ground. DRIVING THE I-Q BASEBAND GAIN CONTROLS The I and Q gain control inputs to the ADL5390 set the gain for each channel. These inputs are differential and should normally have a common-mode level of 0.5 V. However, when differen- tially driven, the common mode can vary from 250 mV to 750 mV while still allowing full gain control ...

Page 14

... The full-scale current is user programmable and is usually set to 20 mA, that is each output swings from mA. The basic interface between the AD9777 DAC outputs and the ADL5390 I and Q gain control inputs is shown in Figure 32. Resistors R1 and R2 (R1 = R2) set the dc bias level according to the following equation: Bias Level = Average Output Current × ...

Page 15

... MIN GAIN < –30dB –0.5 Figure 34. Vector Gain Representation The ADL5390 can be used as a vector modulator by driving the RF I and Q inputs single-ended through a 90 controlling the relative amounts of I and Q components that are summed, continuous magnitude and phase control of the gain is possible ...

Page 16

... In contrast to Figure 36, Figure 37 shows that for a fixed input power, ACP remains fairly constant as gain and phase are changed (this is not true for very high RF input powers) until –30 the noise floor of the ADL5390 becomes the dominant con- tributor to the measured ACP. –40 –50 – ...

Page 17

... QUADRATURE MODULATOR The ADL5390 can be used as a quadrature modulator by driving the RF I and Q inputs (INPI and INPQ) single-ended through phase splitter to serve as the LO input. I/Q modulation is applied to the baseband I and Q gain control inputs (IBBP/IBBM and QBBP/QBBM). A simplified schematic is shown in Figure 38. ...

Page 18

... UPPER TOTAL –18.13dBm 2ND ALTERNATE CHANNEL LOWER UPPER Figure 41. ADL5390 as a Quadrature Modulator with the Use of an External 90° Phase Splitter, RF/LO Power = −1 dBm and Gain Control Inputs Driven Differentially with 0.353 V , 3-Carrier CDMA2000 I/Q Data P-P –69 NOISE (dBc) - 8MHz OFFSET - 1MHz RBW – ...

Page 19

... In this case, a bias level is provided to the unused input from Potentiometer R10 by installing either W1 or W2. Setting SW1 in Position B disables the ADL5390 output amplifier. With SW1 set to Position A, the output amplifier is enabled. With SW1 set to Position A, an external voltage signal, such as a pulse, can be applied to the DSOP SMA connector to exercise the output amplifier enable/disable function ...

Page 20

... C2, C1 and Q Channel RF Input Interface. The single-ended impedance to the C5, C6, R22 ADL5390 RF inputs is 200 Ω. Shunt terminations R2 and R22 of 66.5 Ω bring the impedances to 50 Ω. C2 and C5 are dc blocks. C1 and C6 are used to ac-couple the unused side of the differential inputs to common. R4, R6, R5, C4, C7 Power Supply Decoupling ...

Page 21

... R1 R3 C20 (OPEN) (OPEN) 0.1µF QBBP QBBM Figure 44. Evaluation Board Schematic Rev Page GND TEST POINT TEST POINT B SW1 R8 A 10kΩ C18 10nF C17 L4 L3 ETC1-1-13 10nF 120nH (M/A-COM 0.1µF ADL5390 DSOP RFOP ...

Page 22

... ADL5390 Figure 45. Component Side Layout Figure 46. Component Side Silkscreen Rev Page ...

Page 23

... Dimensions shown in millimeters Package Description 24-Lead Lead Frame Chip Scale Package (LFCSP) 24-Lead Lead Frame Chip Scale Package (LFCSP) Evaluation Board Rev Page 0.60 MAX PIN 1 INDICATOR 2.45 EXPOSED 2. PAD (BO TTOMVIEW) 2. 0.23 MIN 2.50 REF Package Option CP-24-2 CP-24-2 ADL5390 Order Multiple 64 1,500 1 ...

Page 24

... ADL5390 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and regis- tered trademarks are the property of their respective owners. D04954–0–10/04(0) Rev Page ...

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