z87010 ZiLOG Semiconductor, z87010 Datasheet
z87010
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z87010 Summary of contents
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... MHz frequency-hopping spread spectrum cordless telephone in conformance with United States FCC regulations for unlicensed operation. The Z87010 and Z87L10 are distinct 5V and 3.3V versions of the ADPCM Audio Encoder/Decoder. For the sake of brevity, all subsequent references to the Z87010 in this document also are applicable to the Z87L10, unless spe- cifically noted ...
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... Z87010/Z87L10 Audio Encoder/Decoders GENERAL DESCRIPTION (Continued) ICs. As configured by the Zilog-provided embedded soft- ware for digital cordless phones, the Z87010 supports a low-cost 8-bit -law telephone CODEC. The Z87010 is to EXT 0-15 /RDYE 16-Bit I/O ER//W Interface /EI EA0-2 Wait State Generator 13-Bit Timer Notes: All signals with a preceding front slash, ‘/’, are active Low, e.g., B//W (WORD is active Low) ...
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... PIN DESCRIPTION VSS EXT0 EXT1 EXT2 VSS RXD EXT12 EXT13 EXT14 VSS EXT15 DS96WRL0601 Z87010 Figure 2. 44-Pin PLCC Pin Assignments Z87010/Z87L10 Audio Encoder/Decoders 39 EA0 /RESET WAIT RD//WR VDD SCLK UI0 UI1 /INT1 /INT2 29 EXT11 2 2-3 ...
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... Z87010/Z87L10 Audio Encoder/Decoders PIN DESCRIPTION (Continued) No. Symbol 1 HALT 2 FS0 3 /INT0 4-5 UO0-UO1 6 FS1 7,11,16,20, 8-10 EXT0-EXT2 12 RXD 13-15 EXT12-EXT14 17 EXT15 18-19 EXT3-EXT4 21-23 EXT5-EXT7 24 TXD 25-26 EXT8-EXT9 28-29 EXT10-EXT11 30 /INT2 31 /INT1 32 UI1 33 UI0 34 SCLK 35, RD//WR 37 WAIT 38 /RESET 39-41 EA0-EA2 43 /DS 44 CLK Note: *Defined input or output by interface mode selection 2-4 Table 1. 44-Pin PLCC Pin Identifi ...
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... Zilog EXT12 EXT13 EXT14 EXT15 DS96WRL0601 33 VSS 34 EXT0 EXT1 EXT2 VSS RXD Z87010 VSS 44 1 Figure 3. 44-Pin QFP Pin Assignments Z87010/Z87L10 Audio Encoder/Decoders 23 22 EA0 /RES /RDYE ER//W VDD SCLK UI0 UI1 /INT1 /INT2 12 EXT11 11 2 2-5 ...
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... Z87010/Z87L10 Audio Encoder/Decoders PIN DESCRIPTION (Continued) No. Symbol 1-2 EXT3-EXT4 3, 4-6 EXT5-EXT7 7 TXD 8-9 EXT8-EXT9 11-12 EXT10-EXT11 13 /INT2 14 /INT1 15 UI1 16 UI0 17 SCLK 18, ER//W 20 /RDYE 21 /RES 22-24 EA0-EA2 26 / HALT 29 FS0 30 /INT0 31-32 U00-U01 33 FS1 35-37 EXT0-EXT2 RXD 40-42 EXT12-EXT14 EXT15 Note: *Input or output is defined by interface mode selection. ...
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... The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to ground. Positive current flows into the referenced pin (Figure 4). Standard test conditions are as follows: 3.0V V 3.6V (Z87L10) DD 4.5V V 5.5V (Z87010 - DS96WRL0601 Stresses greater than those listed under Absolute Maxi- Max ...
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... Z87010/Z87L10 Audio Encoder/Decoders DC ELECTRICAL CHARACTERISTICS V = 4.5V to 5.5V (Z87010) DD Symbol Parameter I Supply Current Power DC Consumption V Input High Level IH V Input Low Level IL I Input Leakage L V Output High Voltage OH V Output Low Voltage OL I Output Floating FL Leakage Current Note: 5. The following specifications are pin specific: EA0-2 has I 6 ...
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... THH Halt Hold Time to CLK Rise DS96WRL0601 Min (ns – – Z87010/Z87L10 Audio Encoder/Decoders 2 Max (ns) – – – – – _ – – – 2-9 ...
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... Z87010/Z87L10 Audio Encoder/Decoders AC TIMING DIAGRAMS CK /EI ER//W EXT (15:0) EA (2:0) /RDYE 2-10 TCY PWW TXVD TEAD TIEDF TIEDR EXT Bus: Output Valid Data Out Valid Address Out RDYS Figure 5. Write to External Device Timing TXWH TEAD TEAD RDYH DS96WRL0601 Zilog ...
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... Zilog CK TEAD /EI ER//W EXT (15:0) EA (2:0) /RDYE DS96WRL0601 TCY PWW TXRS TIEDF TIED EXT Bus: Input Valid Data In Valid Address Out RDYS Figure 6. Read From External Device Timing Z87010/Z87L10 Audio Encoder/Decoders TXRH TEAD RDYH 2 2-11 ...
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... Z87010/Z87L10 Audio Encoder/Decoders AC TIMING DIAGRAMS (Continued) CK Interrupt HALT Internal SCLK SDCR SCLK down from CLK rise SUCR SCLK up from CLK rise FDCR FS0, FS1 down from SCLK rise FUCR FS0, FS1 up from SCLK rise TDSR TXD down from SCLK rise TUSR ...
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... Zilog CLOCK SCLK FS0, 1 TXD RXD DS96WRL0601 SDCR TCY SUSR FUCR TUSR TDSR RSV RH Figure 8. CODEC Interface Timing Z87010/Z87L10 Audio Encoder/Decoders FDCR 2 2-13 ...
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... INT1 and INT2 are shared with internal Z87010 peripher- als. INT1 is dedicated to the CODEC interface if enabled. INT2 services the 13-bit Timer if enabled. In the Z87010 standard software configuration, INT0 and INT2 are not used; INT1 is used by the CODEC interface. /RES Reset (input, active Low). This pin controls the asyn- chronous reset signal ...
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... However, INT1 is dedicated to the CODEC interface and INT2 is dedicated to the 13-bit timer if these peripherals are enabled. User Inputs. The Z87010 has two inputs, UI0 and UI1, which may be used by Jump and Call instructions. The Jump or Call tests one of these pins and if appropriate, jumps to a new location ...
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... Z87010/Z87L10 Audio Encoder/Decoders CODEC INTERFACE The CODEC interface provides direct-connect capabilities for standard 8-bit PCM CODECs with hardware compression. Internal registers EXT5, EXT6 and EXT7 are used to program the CODEC mode. One serial clock and 16 EXT5-1 CLKIN 16 EXT5-2 CLKIN CLKIN TXD ...
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... Zilog Assuming an input clock of 16.384 MHz, SCLK is pro- grammed by the Z87010 embedded software for 2.048 MHz. TXD (Serial Output to CODEC) The TXD line provides 8-bit data transfers. Each bit is clocked out of the processor by the rising edge of the SCLK, with the MSB transmitted first. ...
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... The CODEC interface timing is independent of the proces- sor clock when external mode is chosen. This feature pro- vides the capability for an external device to control the transfer of data to the Z87010. The Frame Sync signal en- velopes the transmitted data (Figure 10), therefore care must be taken to ensure proper sync signal timing. In the ...
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... Figure 13. CODEC Interface Control Register Z87010/Z87L10 Audio Encoder/Decoders D1 D0 SCLK Prescaler (up-counter) SCLK/FSYNC Ratio Prescaler (up-counter) CODEC Mode 01 Reserved 10 Reserved 11 Reserved FSYNC 0 External Source* 1 Internal Source CODEC 0 Disable/Enable 0 = Disable Enable ...
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... Read and/or write cycles can be independently lengthened for each register, by setting register EXT7-2 accordingly. See Figure 9 for detailed description of EXT7-2. The Z87010 software uses one wait state on all external register accesses. For additional wait states, a dedicate pin (/RDYE) can be held high. The /RDYE pin is monitored only during execu- tion of a Read or Write Instruction to external peripherals ...
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... Accessing the CODEC Interface Registers EXT5, EXT6 AND EXT7 host double buffered registers. External serial CODEC data is transferred from pin RxD to the Z87010 CODEC interface registers EXT5-2. At the same time, the data present in EXT5-2 is serially trans- ferred to the external CODEC through pin TxD. ...
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