tda4855 NXP Semiconductors, tda4855 Datasheet
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... DATA SHEET TDA4855 Autosync Deflection Controller (ASDC) Preliminary specification File under Integrated Circuits, IC02 INTEGRATED CIRCUITS 1996 Jul 18 ...
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... Prepared for additional DC controls of vertical linearity, EW-corner, EW pin balance, EW parallelogram, vertical focus by extended application. GENERAL DESCRIPTION The TDA4855 is a high performance and efficient solution for autosync monitors. The concept is fully DC controllable and can be used in applications with a microcontroller and stand-alone in rock bottom solutions. ...
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... ORDERING INFORMATION TYPE NUMBER NAME TDA4855 SDIP32 plastic shrink dual in-line package; 32 leads (400 mil) 1996 Jul 18 PARAMETER PACKAGE DESCRIPTION 3 Preliminary specification MIN. TYP. MAX. 9 10.5 60 100 11 0.15 3.0 0.2 4.0 0 TDA4855 UNIT VERSION SOT232-1 ...
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... Philips Semiconductors Autosync Deflection Controller (ASDC) BLOCK DIAGRAM 1996 Jul 18 4 Preliminary specification TDA4855 pagewidth full handbook, ...
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... HFLB 1 XRAY 2 BOP 3 BSENS 4 BIN 5 BDRV 6 HDRV 7 PGND 8 TDA4855 FOCUS 10 EWDRV 11 VOUT2 12 VOUT1 13 VSYNC 14 HSYNC 15 CLBL 16 Fig.2 Pin configuration. 5 Preliminary specification TDA4855 32 EWWID 31 HPLL2 30 HPOS 29 HCAP 28 HREF 27 HBUF 26 HPLL1 25 SGND 24 VCAP 23 VREF 22 VAGC 21 EWPAR 20 EWTRP 19 VSCOR 18 VAMP 17 VPOS MBG549 ...
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... These automatic VGA presets are activated only if the current ratio I /I exceeds a fixed value HBUF HREF (see Chapter “Characteristics”). Thus it is possible to disable this function for a part of the frequency range or even completely. Table 1 VGA modes HORIZONTAL/VERTICAL SYNC MODE VGA350 + VGA400 VGA480 + 6 Preliminary specification TDA4855 POLARITY + + ...
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... S max f S min 28.93 kHz = ----------------- - = 1.087 and R can be calculated with the HREF HBUF 74 kHz k 1.091 k = ------------------------------------- - = f kHz max R 1.19 n HREF = -------------------------------------------- - = 2. – f max n 2.35 = ---------- - = f min TDA4855 have to be max and the HBUF . It is also HBUF for f min (2 8.69% ...
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... HPOS 8 Preliminary specification (see Fig.14 determined by the osc(V) connected to pin 23 and the capacitor VREF connected to pin 24. The value of R should be used to select the VCAP 1 = ---------------------------------------------------------- - 10 VREF VCAP TDA4855 has CC is not only VREF must not VREF ...
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... B+ control amplifier BIN (pin 5). This mode used for driving EW modulators which require a voltage independent of the line frequency. EWTRP (pin 20) is used to adjust the amount of trapezium correction in the EW drive waveform. 9 Preliminary specification TDA4855 is in the specified VPOS ...
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... This behaviour allows a definition of the maximum duty cycle of the B+ control drive pulse by the relationship of charge current to discharge current. to the rising edge of 10 Preliminary specification TDA4855 . is reached. This level STOP(BSENS) , the discharge circuit will be RESTART(BSENS) ...
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... HPLL2 will lead to a slightly different sequence. Here the activation of all functions is influenced only by the voltage at HPLL2 (see Fig.15). Application hint: Internal discharge of the capacitor at HPLL2 will only be performed, if the protection mode was activated via the supply voltage or X-ray protection. 11 Preliminary specification TDA4855 ...
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... In accordance with “URF-4-2-59/601” ; EMC emission/immunity test in accordance with “DIS 1000 4.6” (IEC 801.6) SYMBOL PARAMETER V emission test EMC immunity test Note 1. Tests are performed with application reference board. Tests with other boards will have different results. 1996 Jul 18 PARAMETER PARAMETER CONDITIONS note 1 note 1 12 Preliminary specification TDA4855 MIN. MAX. 0.5 +16 0.5 +6.0 0.5 +6.5 0.5 +8.0 0.5 +6.5 0.5 +16 0.5 +6.0 ...
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... 3.345 mA HREF SYNC 13 Preliminary specification MIN. TYP. 15)] PIN 1.7 1 VIDEO NEGATIVE SYNC POLARITY 300 90 120 1.1 1.28 1.7 2.4 clamp(HSYNC) 0 3.9 5.7 2.5 3.8 1.7 1.2 1.4 5.5 V TDA4855 MAX. UNIT V 1.6 V 500 ns 500 ns s 200 150 mV 1 1500 1 6 ...
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... V CLBL clamping pulse triggered on trailing edge of horizontal sync measured at V CLBL notes 1 and 2 VGA presets active VGA presets disabled CLBL 14 Preliminary specification TDA4855 MIN. TYP. MAX. HSYNC ( 15) PIN 0.7 1.0 1.35 4.4 4.8 5.2 300 300 0.3 1 0.6 0.7 0.8 4.32 4 ...
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... HSHIFT I = 135 A HSHIFT HPOS = +10.5% 110 HPOS = 10.5% note 30.53 HBUF HREF nF; note 5 HCAP 100 2.43 maximum advance 36 minimum advance HPOS (pin 30) grounded V 3.7 V HPLL2 15 Preliminary specification TDA4855 TYP. MAX. UNIT 5.6 V 2.5 V 4.0 mA 10.5 % +10.5 % 120 135 5.1 V 0.1 V 31.45 32.39 kHz 3 ...
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... Fig mA; HDRV kHz; see Fig 6. XRAY V 6. XRAY VREF C = 100 nF VCAP constant amplitude; notes 8, 9 and 10 VGA presets active VGA presets disabled 16 Preliminary specification TDA4855 MIN. TYP. MAX. 5.5 0. 2.8 0.3 0 46.3 47.7 46.6 48 49.4 6.14 6.38 6.64 10 500 ...
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... Figs [VSCOR ( note 11 VSCOR I = 135 A; VSCOR note 11 maximum VSCOR note 13 17 Preliminary specification MIN. TYP. 60 100 110 120 0 5.0 2.25 2.5 116.8 102.2 100.0 11.5 +11.5 110 120 0 5.0 0 19)] PIN 2 46 110 120 0 5.0 TDA4855 MAX. UNIT % % 135 2. 135 0 135 145 mV ...
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... A; EWPAR note 11 (see Figs [EWWID ( PIN I = 135 A; EWWID note note 11 EWWID 18 Preliminary specification MIN. TYP. 0.76 0.85 0.54 0 1.05 1 7.0 21)] PIN 0.05 3 110 120 0 5.0 32)] 0.1 4.2 0 110 120 5.0 TDA4855 MAX. UNIT 0.94 mA 0.66 mA 4.2 V 2.5 % 1 600 135 135 A V ...
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... 2.341 mA; HREF kHz; note 16 H function disabled; note 16 2.7 tracking FOCUS FOCUS 19 Preliminary specification MIN. TYP. 20)] PIN 0.5 +0.5 110 120 0 5 1.3 1.45 2.7 3.0 3.0 0 0.03 1 0.9 1.0 3.65 4.0 TDA4855 MAX. UNIT V V 135 0.1 V 145 mV 80 kHz 1.6 V 3 1.1 V 4.4 V ...
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... I = 0.5 mA BSENS V 2.5 V BSENS fault condition kHz 20 Preliminary specification MIN. TYP. 0 2.37 2.5 0.4 5 5.3 500 4 250 500 = 3 V 0.85 1.0 4.5 6 1.2 1 TDA4855 MAX. UNIT 300 1.15 V 7 ...
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... HREF linear sawtooth with the same modulation depth can be recovered Preliminary specification = 60 A). Then the PLL1 filter HPOS = 1 : 2.5) can be made usable by choosing HBUF HREF – ------ - In ------------ - with ‘d’ being the modulation TDA4855 exceeds the ...
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... VOUT1 VOUT2 1996 Jul 18 . The EWDRV low level of 1.2 V remains fixed. HREF MBG590 handbook, halfpage ( Preliminary specification = 4.7 nF (from BOP (pin 3) to GND). BOP V EWDRV EWPAR = PAR(EWDRV) Fig function of time. EWDRV TDA4855 MBG591 V PAR(EWDRV) t ...
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... VOUT2 1996 Jul 18 MBG592 handbook, halfpage V EWDRV ( MBG594 handbook, halfpage V EWDRV ( Preliminary specification EWWID = DC(EWDRV) Fig function of time. EWDRV EWTRP = V . TRP(EWDRV) Fig function of time. EWDRV TDA4855 MBG593 V DC(EWDRV) t MBG595 V TRP(EWDRV) t ...
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... HFLB (pin 1) PLL2 control current at HPLL2 (pin 31) line drive pulse at HDRV (pin 7) horizontal focus parabola at FOCUS (pin 10) 1996 Jul PLL2 control range 45 to 48% of line period Fig.9 Pulse diagram for horizontal part. 24 Preliminary specification TDA4855 - vertical blanking level – MBG598 ...
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... VOUT2 (pin 12) EW drive waveform at EWDRV (pin 11) 1996 Jul 18 4.0 V automatic trigger level 3.8 V synchronized trigger level 1.4 V inhibited I VOUT1 I VOUT2 tip-parabola EW parabola 3 V (p-p) maximum DC shift 4 V maximum Fig.10 Pulse diagram for vertical part. 25 Preliminary specification TDA4855 7.0 V maximum LOW level 1.2 V fixed MBG597 ...
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... HSYNC (pin 15) clamping and blanking pulses at CLBL (pin 16) b. Generation of video clamping pulses during vertical sync with serration pulses. Fig.11 Pulse diagrams for composite sync applications. 1996 Jul 18 26 Preliminary specification TDA4855 MGC947 MBG596 ...
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... C BOP 4 Feedback mode application. Fig.12 Application and timing for feedback mode. 27 Preliminary specification BDRV S Q TR1 R Q INVERTING BUFFER DISCHARGE off(min) V RESTART(BSENS) V STOP(BSENS) MBG600 c. Waveforms for fault condition. TDA4855 L D2 HORIZONTAL OUTPUT STAGE R4 MBG599 ...
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... Fig.13 Application and timing for feed forward mode. 28 Preliminary specification HORIZONTAL INVERTING OUTPUT BUFFER Q STAGE Q EHT 3 V BDRV transformer TR1 t off (discharge time of C BSENS ) c. Waveforms for fault condition. TDA4855 horizontal flyback pulse MOSFET 5 MBG601 V RESTART(BSENS) V STOP(BSENS) MBG602 ...
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... BDRV floating VOUT1 and VOUT2 floating b. Shut-down sequence. Fig.14 Start-up sequence and shut-down sequence. 29 Preliminary specification 8.5 V continuous blanking off PLL2 enabled V HPLL2 frequency detector enabled V CC 8.2 V and V HPLL2 3.7 V (1) MBG554 5.6 V HDRV floating 4.0 V continuous blanking disappears time TDA4855 MBG555 V CC 8.5 V and 4.4 V time ...
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... PLL2 disabled frequency detector disabled 3.7 V HDRV duty factor begins to decrease BDRV floating VOUT1 and VOUT2 floating b. PLL2 shut-down sequence. Fig.15 PLL2 soft start sequence. 30 Preliminary specification TDA4855 MBG553 4.4 V continuous blanking off PLL2 enabled frequency detector enabled time MBG552 0.5 V HDRV floating ...
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... VCAP I I – Which means -------------- – 1 Vertical linearity error = 1 max – -------------- 1996 Jul 18 (1) I VOUT ( A) 415 ( 415 – -------------- I 0 Fig.16 Definition of vertical linearity error. 31 Preliminary specification MBG551 ( ( VCAP TDA4855 ...
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... VSCOR (pin 19). Fig.17 Superimposed waveforms at pins 19 and 20 with pins 17, 18 32. 1996 Jul 18 VPOS handbook, halfpage VAMP EWPAR EWWID 17, 18, 21 120 mV (p-p) MBG556 32 Preliminary specification TDA4855 VPOS VAMP EWPAR EWWID EWTRP 20 17, 18, 21 MBG557 b. EWTRP (pin 20). ...
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... For optimum performance of the TDA4855 the ground paths must be routed as shown. Only one connection to other grounds on the PCB is allowed. 1996 Jul 18 further connections to other components or ground paths are not allowed TDA4855 ...
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... Philips Semiconductors Autosync Deflection Controller (ASDC) INTERNAL CIRCUITRY Table 5 Internal circuitry of Fig.1 PIN SYMBOL 1 HFLB 2 XRAY 3 BOP 1996 Jul 18 INTERNAL CIRCUIT 1 MBG562 3 34 Preliminary specification TDA4855 MBG561 6.25 V 5.3 V MBG563 ...
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... Philips Semiconductors Autosync Deflection Controller (ASDC) PIN SYMBOL 4 BSENS 5 BIN 6 BDRV 7 HDRV 8 PGND 1996 Jul MBG565 power ground, connected to substrate 35 Preliminary specification INTERNAL CIRCUIT MBG564 6 MBG566 7 MBG567 9 MBG568 TDA4855 ...
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... Philips Semiconductors Autosync Deflection Controller (ASDC) PIN SYMBOL 10 FOCUS 11 EWDRV 12 VOUT2 13 VOUT1 1996 Jul 18 INTERNAL CIRCUIT MBG569 108 11 108 MBG570 MBG571 12 MBG572 13 36 Preliminary specification TDA4855 ...
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... Philips Semiconductors Autosync Deflection Controller (ASDC) PIN SYMBOL 14 VSYNC 15 HSYNC 16 CLBL 17 VPOS 1996 Jul 18 INTERNAL CIRCUIT 100 1 7 MBG575 7 MBG576 37 Preliminary specification TDA4855 MBG573 1.4 V MBG574 5 V ...
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... Philips Semiconductors Autosync Deflection Controller (ASDC) PIN SYMBOL 18 VAMP 19 VSCOR 20 EWTRP 1996 Jul 18 INTERNAL CIRCUIT MBG577 MBG578 MBG579 38 Preliminary specification TDA4855 ...
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... Philips Semiconductors Autosync Deflection Controller (ASDC) PIN SYMBOL 21 EWPAR 22 VAGC 23 VREF 24 VCAP 25 SGND 1996 Jul signal ground 39 Preliminary specification INTERNAL CIRCUIT MBG580 MBG581 3 V MBG582 MBG583 TDA4855 ...
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... Philips Semiconductors Autosync Deflection Controller (ASDC) PIN SYMBOL 26 HPLL1 27 HBUF 28 HREF 29 HCAP 30 HPOS 1996 Jul 18 INTERNAL CIRCUIT 1 MBG586 40 Preliminary specification TDA4855 MBG589 MBG584 2.525 V MBG585 4.3 V ...
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... Electrostatic discharge (ESD) protection pin Fig.19 ESD protection for pins and 16. 1996 Jul 18 INTERNAL CIRCUIT 7 7 MBG559 Fig.20 ESD protection for pins and 41 Preliminary specification TDA4855 HFLB MBG587 MBG588 pin 7.3 V 7.3 V MBG560 26 to 32. ...
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... IEC SOT232-1 1996 Jul scale (1) ( 1.3 0.53 0.32 29.4 9.1 0.8 0.40 0.23 28.5 8.7 REFERENCES JEDEC EIAJ 42 Preliminary specification 3.2 10.7 12.2 1.778 10.16 2.8 10.2 10.5 EUROPEAN PROJECTION TDA4855 SOT232 ( max. 0.18 1.6 ISSUE DATE 92-11-17 95-02-04 ...
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... If the temperature of the soldering iron bit is less than 300 C it may remain in contact for seconds. If the bit temperature is between 300 and 400 C, contact may seconds. 43 Preliminary specification TDA4855 ). If the stg max ...
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... Tel. +1 800 234 7381, Fax. +1 708 296 8556 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 825 344, Fax.+381 11 635 777 Internet: http://www.semiconductors.philips.com/ps/ (1) TDA4855_1 June 26, 1996 11:51 am Date of release: 1996 Jul 18 Document order number: SCA50 9397 750 00973 ...