74lcx16240mtdx-nl Fairchild Semiconductor, 74lcx16240mtdx-nl Datasheet
74lcx16240mtdx-nl
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74lcx16240mtdx-nl Summary of contents
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... Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram ¥ GTO is a trademark of Fairchild Semiconductor Corporation. © 2005 Fairchild Semiconductor Corporation Features 5V tolerant inputs and outputs 2.3V to 3.6V V ...
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Truth Tables Inputs OE I – Inputs OE I – HIGH Voltage Level L LOW Voltage Level X Immaterial Z High ...
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Absolute Maximum Ratings Symbol Parameter V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Source/Sink Current Supply ...
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DC Electrical Characteristics Symbol Parameter I Quiescent Supply Current Increase in I per Input CC CC Note 5: Outputs disabled or 3-STATE only. AC Electrical Characteristics Symbol Parameter t Propagation Delay PHL t Data to Output PLH ...
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AC LOADING and WAVEFORMS FIGURE 1. AC Test Circuit (C t PLH t PZL t PZH Waveform for Inverting and Non-Inverting Functions Propagation Delay. Pulse Width and t rec 3-STATE Output Low Enable and Disable Times for Logic (Input Characteristics; ...
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Schematic Diagram Generic for LCX Family www.fairchildsemi.com 6 ...
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Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A 7 www.fairchildsemi.com ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...