74lcx16543 Fairchild Semiconductor, 74lcx16543 Datasheet
74lcx16543
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74lcx16543 Summary of contents
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... MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide 74LCX16543MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. ...
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Pin Descriptions Pin Names OEAB n OEBA n CEAB n CEBA n LEAB n LEBA n A – – Data I/O Control Table Inputs CEAB LEAB HIGH Voltage ...
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Logic Diagrams Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. Byte 1 (0:7) Byte 2 (8:15) 3 www.fairchildsemi.com ...
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Absolute Maximum Ratings Symbol Parameter V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Source/Sink Current Supply ...
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DC Electrical Characteristics Symbol Parameter I Quiescent Supply Current CC I Increase in I per Input CC CC Note 5: Outputs in disabled or 3-STATE only. AC Electrical Characteristics Symbol Parameter t Propagation Delay PHL ...
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AC LOADING and WAVEFORMS FIGURE 1. AC Test Circuit (C Waveform for Inverting and Non-Inverting Functions Propagation Delay. Pulse Width and t rec 3-STATE Output Low Enable and Disable Times for Logic (Input Characteristics; f =1MHz, t Symbol V mi ...
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Schematic Diagram Generic for LCX Family 7 www.fairchildsemi.com ...
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Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide www.fairchildsemi.com Package Number MS56A 8 ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...