74abt841pwdh NXP Semiconductors, 74abt841pwdh Datasheet

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74abt841pwdh

Manufacturer Part Number
74abt841pwdh
Description
10-bit Bus Interface Latch 3-state
Manufacturer
NXP Semiconductors
Datasheet
1.74ABT841PWDH.pdf (6 pages)
Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
ORDERING INFORMATION
PIN CONFIGURATION
24-Pin Plastic DIP
24-Pin plastic SO
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
1995 Sep 06
High speed parallel latches
Extra data width for wide address/data paths or buses carrying
parity
Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
Slim DIP 300 mil package
Broadside pinout
Output capability: +64mA/–32mA
Latch-up protection exceeds 500mA per Jedec Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
Power-up 3-State
Power-up reset
10-bit bus interface latch (3-State)
SYMBOL
C
I
t
t
C
PLH
PHL
CCZ
OUT
IN
PACKAGES
Propagation delay
Dn to Qn
Input capacitance
Output capacitance
Total supply current
GND
OE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
10
11
12
1
2
3
4
5
6
7
8
9
TOP VIEW
PARAMETER
TEMPERATURE RANGE
24
23
22
21
20
19
18
17
16
15
14
13
–40 C to +85 C
–40 C to +85 C
–40 C to +85 C
–40 C to +85 C
V
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
LE
CC
SA00247
C
V
Outputs disabled;
V
Outputs disabled; V
I
O
L
= 0V or V
= 50pF; V
= 0V or V
OUTSIDE NORTH AMERICA
1
DESCRIPTION
The 74ABT841 Bus interface register is designed to provide extra
data width for wider data/address paths of buses carrying parity.
The 74ABT841 consists of ten D-type latches with 3-State outputs.
The flip-flops appear transparent to the data when Latch Enable
(LE) is High. This allows asynchronous operation, as the output
transition follows the data in transition. On the LE High-to-Low
transition, the data that meets the setup and hold time is latched.
Data appears on the bus when the Output Enable (OE) is Low.
When OE is High the output is in the High-impedance state.
PIN DESCRIPTION
T
74ABT841 PW
74ABT841 DB
CC
74ABT841 N
74ABT841 D
amb
CC
CC
23, 22, 21, 20, 19,
18, 17, 16, 15, 14
PIN NUMBER
7, 8, 9, 10, 11
CONDITIONS
= 5V
= 25 C; GND = 0V
2, 3, 4, 5, 6,
CC
13
12
24
1
= 5.5V
SYMBOL
NORTH AMERICA
Q0-Q9
74ABT841PW DH
D0-D9
GND
V
OE
74ABT841 DB
LE
CC
74ABT841 N
74ABT841 D
Output enable input
(active-Low)
Data inputs
Data outputs
Latch enable input (active
falling edge)
Ground (0V)
Positive supply voltage
TYPICAL
500
4.1
4
7
Product specification
74ABT841
FUNCTION
DWG NUMBER
853-1628 15703
SOT222-1
SOT137-1
SOT340-1
SOT355-1
UNIT
pF
pF
nA
ns

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74abt841pwdh Summary of contents

Page 1

Philips Semiconductors 10-bit bus interface latch (3-State) FEATURES High speed parallel latches Extra data width for wide address/data paths or buses carrying parity Ideal where high speed, light loading, or increased fan-in are required with MOS microprocessors Slim DIP 300 ...

Page 2

Philips Semiconductors 10-bit bus interface latch (3-State) LOGIC SYMBOL ...

Page 3

Philips Semiconductors 10-bit bus interface latch (3-State) LOGIC DIAGRAM ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER V DC ...

Page 4

Philips Semiconductors 10-bit bus interface latch (3-State) DC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER V Input clamp voltage IK V High-level output voltage OH V Low-level output voltage OL Power-up output low V RST 3 voltage I Input leakage Control pins I ...

Page 5

Philips Semiconductors 10-bit bus interface latch (3-State) AC SETUP REQUIREMENTS GND = 0V 2.5ns 50pF 500 SYMBOL PARAMETER t (H) Setup time, High or Low s t (L) ...

Page 6

Philips Semiconductors 10-bit bus interface latch (3-State) TEST CIRCUIT AND WAVEFORM OUT PULSE D.U.T. GENERATOR R T Test Circuit for 3-State Outputs SWITCH POSITION TEST SWITCH t closed PLZ t closed PZL All other open ...

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