74abt821pw NXP Semiconductors, 74abt821pw Datasheet

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74abt821pw

Manufacturer Part Number
74abt821pw
Description
10-bit D-type Flip-flop; Positive-edge Trigger 3-state
Manufacturer
NXP Semiconductors
Datasheet
1.74ABT821PW.pdf (17 pages)
1. General description
2. Features
The 74ABT821 high-performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT821 bus interface register is designed to eliminate the extra packages required
to buffer existing registers and provide extra data width for wider data/address paths of
buses carrying parity.
The 74ABT821 is a buffered 10-bit wide version of the 74ABT374A and 74ABT534A
functions.
The 74ABT821 is a 10-bit, edge triggered register coupled to ten 3-state output buffers.
The two sections of the device are controlled independently by the clock (CP) and output
enable (OE) control gates.
The register is fully edge triggered. The state of each D input, one set-up time before the
LOW-to-HIGH clock transition is transferred to the corresponding output Q of the flip-flop.
The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS
memories, or MOS microprocessors.
The active LOW output enable (OE) controls all ten 3-state buffers independent of the
register operation. When OE is LOW, the data in the register appears at the outputs.
When OE is HIGH, the outputs are in high-impedance OFF-state, which means they will
neither drive nor load the bus.
74ABT821
10-bit D-type flip-flop; positive-edge trigger; 3-state
Rev. 02 — 12 April 2005
High-speed parallel registers with positive-edge triggered D-type flip-flops
Ideal where high speed, light loading, or increased fan-in are required with MOS
microprocessors
Output capability: +64 mA and 32 mA
Power-on 3-state
Power-on reset
Latch-up protection:
ESD protection:
JESD78: exceeds 500 mA
MIL STD 883 method 3015: exceeds 2000 V
Machine model: exceeds 200 V
Product data sheet

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74abt821pw Summary of contents

Page 1

D-type flip-flop; positive-edge trigger; 3-state Rev. 02 — 12 April 2005 1. General description The 74ABT821 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT821 bus interface register ...

Page 2

... Type number Package Temperature range Name 74ABT821D +85 C 74ABT821N +85 C 74ABT821DB +85 C 74ABT821PW + Functional diagram 13 1 Fig 1. Logic symbol 9397 750 14867 Product data sheet 10-bit D-type flip-flop; positive-edge trigger; 3-state Quick reference data = 25 C ...

Page 3

Philips Semiconductors Fig 3. Logic diagram 6. Pinning information 6.1 Pinning Fig 4. Pin configuration 6.2 Pin description Table 3: Symbol OE ...

Page 4

Philips Semiconductors Table 3: Symbol D8 D9 GND Functional description 7.1 Function table Table 4: Operating mode Load and read register Hold Disable outputs [1] H ...

Page 5

Philips Semiconductors 8. Limiting values Table 5: In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol ...

Page 6

Philips Semiconductors 10. Static characteristics Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter amb V input diode voltage IK V HIGH-level output voltage OH V ...

Page 7

Philips Semiconductors Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter I 3-state output current OZ I output HIGH-state leakage CEX current I output current O I quiescent supply current ...

Page 8

Philips Semiconductors Table 8: Dynamic characteristics GND = 0 V; for test circuit see Figure Symbol Parameter t output enable time to LOW-level PZL t output disable time from HIGH-level PHZ t output disable time from LOW-level PLZ t set-up ...

Page 9

Philips Semiconductors Fig 7. 3-state output (Qn) enable and disable times 9397 750 14867 Product data sheet 10-bit D-type flip-flop; positive-edge trigger; 3-state input V M GND t PZL Qn output PZH V OH ...

Page 10

Philips Semiconductors a. Input pulse definition b. Test circuit Fig 8. Load circuitry for switching times Table 9: Input V I 3.0 V 9397 750 14867 Product data sheet 10-bit D-type flip-flop; positive-edge trigger; 3-state negative ...

Page 11

Philips Semiconductors 13. Package outline SO24: plastic small outline package; 24 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT ...

Page 12

Philips Semiconductors DIP24: plastic dual in-line package; 24 leads (300 mil) seating plane pin 1 index 1 DIMENSIONS (mm dimensions are derived from the original inch dimensions UNIT max. min. max. mm ...

Page 13

Philips Semiconductors SSOP24: plastic shrink small outline package; 24 leads; body width 5 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. ...

Page 14

Philips Semiconductors TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm ...

Page 15

Philips Semiconductors 14. Revision history Table 10: Revision history Document ID Release date 74ABT821_2 20050412 • Modifications: The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors. • Section ...

Page 16

Philips Semiconductors 15. Data sheet status [1] Level Data sheet status Product status I Objective data Development II Preliminary data Qualification III Product data Production [1] Please consult the most recently issued data sheet before initiating or completing a design. ...

Page 17

Philips Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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