74abt646cscx-nl Fairchild Semiconductor, 74abt646cscx-nl Datasheet

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74abt646cscx-nl

Manufacturer Part Number
74abt646cscx-nl
Description
74abt646 Octal Transceivers And Registers With 3-state Outputs
Manufacturer
Fairchild Semiconductor
Datasheet
© 1999 Fairchild Semiconductor Corporation
74ABT646CSC
74ABT646CMSA
74ABT646CMTC
74ABT646
Octal Transceivers and Registers with 3-STATE Outputs
General Description
The ABT646 consists of bus transceiver circuits with 3-
STATE, D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the input bus
or from the internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes
to a high logic level. Control OE and direction pins are pro-
vided to control the transceiver function. In the transceiver
mode, data present at the high impedance port may be
stored in either the A or the B register or in both. The select
controls can multiplex stored and real-time (transparent
mode) data. The direction control determines which bus
will receive data when the enable control OE is Active
LOW. In the isolation mode (control OE HIGH), A data may
be stored in the B register and/or B data may be stored in
the A register.
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Order Number
Package Number
MSA24
MTC24
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-153, 4.4mm Wide
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
DS010978
Features
Pin Descriptions
A
B
CPAB, CPBA
SAB, SBA
OE
DIR
Independent registers for A and B buses
Multiplexed real-time and stored data
A and B output sink capability of 64 mA, source capabil-
ity of 32 mA
Guaranteed output skew
Guaranteed multiple output switching specifications
Output switching specified for both 50 pF and 250 pF
loads
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Guaranteed latchup protection
High impedance glitch free bus loading during entire
power up and power down cycle
Nondestructive hot insertion capability
Pin Names
0
0
–A
–B
7
7
Package Description
Data Register A Inputs/3-STATE Outputs
Data Register B Inputs/3-STATE Outputs
Clock Pulse Inputs
Select Inputs
Output Enable Input
Direction Control Input
April 1992
Revised November 1999
Description
www.fairchildsemi.com

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74abt646cscx-nl Summary of contents

Page 1

... Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram © 1999 Fairchild Semiconductor Corporation Features Independent registers for A and B buses Multiplexed real-time and stored data ...

Page 2

Truth Table Inputs OE DIR CPAB CPBA SAB ...

Page 3

Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com ...

Page 4

Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias V Pin Potential to Ground Pin CC Input Voltage (Note 3) Input Current (Note 5.0 mA Voltage Applied to Any Output in the ...

Page 5

DC Electrical Characteristics Symbol Parameter V Quiet Output Maximum Dynamic V OLP OL V Quiet Output Minimum Dynamic V OLV OL V Minimum HIGH Level Dynamic Output Voltage OHV V Minimum HIGH Level Dynamic Input Voltage IHD V Maximum LOW ...

Page 6

Extended AC Electrical Characteristics (SOIC Package) Symbol Parameter t Propagation Delay PLH t Clock to Bus PHL t Propagation Delay PLH t Bus to Bus PHL t Propagation Delay PLH t SBA or SAB PHL n ...

Page 7

AC Loading *Includes jig and probe capacitance FIGURE 5. Standard AC Test Load Amplitude 3.0V FIGURE 7. Test Input Signal Requirements AC Waveforms FIGURE 8. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 9. Propagation Delay, Pulse Width Waveforms ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number M24B Package Number MSA24 8 ...

Page 9

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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