74abt374cscx-nl Fairchild Semiconductor, 74abt374cscx-nl Datasheet

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74abt374cscx-nl

Manufacturer Part Number
74abt374cscx-nl
Description
Octal D-type Flip-flop With 3-state Outputs
Manufacturer
Fairchild Semiconductor
Datasheet
©1992 Fairchild Semiconductor Corporation
74ABT374 Rev. 1.4
74ABT374
Octal D-Type Flip-Flop with 3-STATE Outputs
Features
I
I
I
I
I
I
I
I
I
I
I
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Pb-Free package per JEDEC J-STD-020B.
Note:
1. Device available in Tape and Reel only.
74ABT374CSC
74ABT374CSCX_NL
74ABT374CSJ
74ABT374CMSA
74ABT374CMTC
Edge-triggered D-type inputs
Buffered positive edge-triggered clock
3-STATE outputs for bus-oriented applications
Output sink capability of 64mA, source capability of
32mA
Guaranteed output skew
Guaranteed multiple output switching specifications
Output switching specified for both 50pF and 250pF
loads
Guaranteed simultaneous switching, noise level and
dynamic threshold performance
Guaranteed latchup protection
High-impedance, glitch-free bus loading during entire
power up and power down cycle
Nondestructive, hot-insertion capability
Order Number
(1)
Package
Number
MSA20
MTC20
M20B
M20B
M20D
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013,
0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013,
0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150,
5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC
MO-153, 4.4mm Wide
General Description
The ABT374 is an octal D-type flip-flop featuring sepa-
rate D-type inputs for each flip-flop and 3-STATE outputs
for bus-oriented applications. A buffered Clock (CP) and
Output Enable (OE) are common to all flip-flops.
Package Description
www.fairchildsemi.com
March 2007
tm

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74abt374cscx-nl Summary of contents

Page 1

... Nondestructive, hot-insertion capability I Ordering Information Package Order Number Number 74ABT374CSC (1) 74ABT374CSCX_NL 74ABT374CSJ 74ABT374CMSA 74ABT374CMTC Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. Pb-Free package per JEDEC J-STD-020B. Note: 1. Device available in Tape and Reel only. ...

Page 2

... Operation of the OE input does not affect the state of the flip-flops. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©1992 Fairchild Semiconductor Corporation 74ABT374 Rev. 1.4 Pin Descriptions Pin Names Description D – ...

Page 3

... Free Air Ambient Temperature A V Supply Voltage CC ∆V / ∆t Minimum Input Edge Rate Data Input Enable Input Clock Input ©1992 Fairchild Semiconductor Corporation 74ABT374 Rev. 1.4 Parameter Parameter 3 Rating –65°C to +150°C –55°C to +125°C –55°C to +150°C –0.5V to +7.0V – ...

Page 4

... Outputs Enabled CCT I /Input CC Outputs 3-STATE Outputs 3-STATE I Dynamic I No Load CCD CC Notes: 3. For 8-bit toggling, I < 0.8mA/MHz. CCD 4. Guaranteed, but not tested. ©1992 Fairchild Semiconductor Corporation 74ABT374 Rev. 1.4 V Conditions CC Recognized HIGH Signal Recognized LOW Signal Min –18mA IN Min –3mA –32mA OH Min ...

Page 5

... Symbol Parameter f Maximum Clock MAX Frequency t Propagation Delay PLH PHL t Output Enable Time PZH t PZL t Output Disable Time PHZ t PLZ ©1992 Fairchild Semiconductor Corporation 74ABT374 Rev. 1.4 Conditions C = 50pF 500Ω 5 25° 5 25° 5 25° ...

Page 6

... LOW-to-HIGH, HIGH-to-LOW, etc.) with 250pF load capacitors in place of the 50pF load capacitors in the standard AC load. 11. The 3-STATE delay Time is dominated by the RC network (500Ω, 250pF) on the output and has been excluded from the datasheet. ©1992 Fairchild Semiconductor Corporation 74ABT374 Rev. 1 +25° – ...

Page 7

... LOW-to-HIGH, HIGH-to-LOW, etc.). Capacitance Symbol Parameter C Input Capacitance IN (17) C Output Capacitance OUT Note: 17 measured at frequency f = 1MHz, per MIL-STD-883, Method 3012. OUT ©1992 Fairchild Semiconductor Corporation 74ABT374 Rev. 1 –40°C to +85° 4.5V–5. (12) 8 Outputs Switching 8 Outputs Switching Max ...

Page 8

... AC Loading *Includes jig and probe capacitance Figure 1. Standard AC Test Load Amplitude Rep. Rate AC Waveforms Figure 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions Figure 5. Propagation Delay, Pulse Width Waveforms ©1992 Fairchild Semiconductor Corporation 74ABT374 Rev. 1.4 Input Pulse Requirements t w 3.0V 1 MHz 500ns Figure 3 ...

Page 9

... Physical Dimensions Dimensions are in inches (millimeters) unless otherwise noted. Figure 8. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide ©1992 Fairchild Semiconductor Corporation 74ABT374 Rev. 1.4 Package Number M20B 9 www.fairchildsemi.com ...

Page 10

... Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 9. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide ©1992 Fairchild Semiconductor Corporation 74ABT374 Rev. 1.4 Package Number M20D 10 www.fairchildsemi.com ...

Page 11

... Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 10. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide ©1992 Fairchild Semiconductor Corporation 74ABT374 Rev. 1.4 Package Number MSA20 11 www.fairchildsemi.com ...

Page 12

... Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 11. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide ©1992 Fairchild Semiconductor Corporation 74ABT374 Rev. 1.4 Package Number MTC20 12 www.fairchildsemi.com ...

Page 13

... TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended exhaustive list of all such trademarks. ® ACEx Across the board. Around the world.¥ ActiveArray¥ Bottomless¥ Build it Now¥ CoolFET¥ ...

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