74abt74 NXP Semiconductors, 74abt74 Datasheet

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74abt74

Manufacturer Part Number
74abt74
Description
Dual D-type Flip-flop
Manufacturer
NXP Semiconductors
Datasheet

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Part Number
Manufacturer
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Part Number:
74abt74D
Manufacturer:
PHILIPS
Quantity:
8 000
Part Number:
74abt74D
Manufacturer:
PHILIPS/飞利浦
Quantity:
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Philips Semiconductors
QUICK REFERENCE DATA
PIN CONFIGURATION
PIN DESCRIPTION
LOGIC SYMBOL
ORDERING INFORMATION
1995 Sep 22
SYMBOL
14-Pin Plastic DIP
14-Pin plastic SO
14-Pin Plastic SSOP Type II
14-Pin Plastic TSSOP Type I
PIN NUMBER
V
GND = Pin 7
1, 2, 3, 4, 10,
Dual D-type flip-flop
t
t
CC
t
t
OSLH
OSHL
C
11, 12, 13
I
PLH
PHL
5, 6, 8, 9
CC
= Pin 14
IN
14
7
PACKAGES
Propagation
delay
CPn to
Qn, Qn
Output to
Output skew
Input
capacitance
Total supply
current
PARAMETER
10
13
11
3
4
1
CPn, SDn
SYMBOL
GND
RDn, Dn,
RD1
CP0
SD1
Qn, Qn
Q0
Q0
D0
GND
V
CC
1
2
3
4
5
6
7
CP0
SD0
RD0
CP1
SD1
RD1
Q0 Q0 Q1 Q1
C
V
V
Outputs disabled;
V
5
L
CC
CC
I
CC
Data inputs
Data outputs
Ground (0V)
Positive supply voltage
CONDITIONS
T
= 0V or V
D0 D1
= 50pF;
6
amb
2
GND = 0V
= 5V
= 5.5V
12
NAME AND FUNCTION
9
= 25 C;
TEMPERATURE RANGE
8
14
13
12
11
10
CC
9
8
–40 C to +85 C
–40 C to +85 C
–40 C to +85 C
–40 C to +85 C
V
RD1
D1
CP1
SD1
Q1
Q1
CC
TYPICAL
3.0
2.5
0.5
50
3
SF00045
SA00359
UNIT
ns
ns
pF
A
OUTSIDE NORTH AMERICA
1
DESCRIPTION
The 74ABT74 is a dual positive edge-triggered D-type flip-flop
featuring individual data, clock, set, and reset inputs; also true and
complementary outputs. Set (SD) and reset (RD) are asynchronous
active low inputs and operate independently of the clock input.
When set and reset are inactive (high), data at the D input is
transferred to the Q and Q outputs on the low-to-high transition of
the clock. Data must be stable just one setup time prior to the
low-to-high transition of the clock for predictable operation. Clock
triggering occurs at a voltage level and is not directly related to the
transition time of the positive-going pulse. Following the hold time
interval, data at the D input may be changed without affecting the
levels of the output.
LOGIC SYMBOL (IEEE/IEC)
LOGIC DIAGRAM
74ABT74 PW
74ABT74 DB
V
GND = Pin 7
74ABT74 N
74ABT74 D
CC
= Pin 14
SD
RD
CP
D
4, 10
1, 13
2, 12
3, 11
12
13
10
11
4
3
2
1
NORTH AMERICA
74ABT74PW DH
1D
S
S
R
2D
R
74ABT74 DB
74ABT74 N
74ABT74 D
C1
C2
&
Product specification
74ABT74
DWG NUMBER
853-1813 15793
5
6
9
8
SOT108-1
SOT337-1
SOT402-1
SOT27-1
5, 9
6, 8
SF00047
SF00048
Q
Q

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74abt74 Summary of contents

Page 1

... C to +85 C 14-Pin Plastic TSSOP Type I – +85 C 1995 Sep 22 DESCRIPTION The 74ABT74 is a dual positive edge-triggered D-type flip-flop featuring individual data, clock, set, and reset inputs; also true and TYPICAL UNIT complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock input ...

Page 2

... This setup is unstable and will change when either set or reset return to the high level. Hold CONDITIONS V < < output in Off or High state output in Low state PARAMETER PARAMETER 2 Product specification 74ABT74 RATING UNIT –0.5 to +7.0 V –18 mA –1.2 to +7.0 V –50 mA –0 –65 to 150 ...

Page 3

... T = +25 C amb WAVEFORM WAVEFORM V = +5.0V CC MIN TYP 2.6 1 2.4 0 –1 –1.4 1.7 1 1.7 3 2.0 2 2.1 3 Product specification 74ABT74 LIMITS T = –40 C amb UNIT UNIT T = +25 C amb to +85 C MIN TYP MAX MIN MAX –0.9 –1.2 –1.2 2.5 2.9 2.5 0.35 0.5 0.5 0.01 1.0 1.0 5.0 100 100 5 –50 –75 –180 –50 – ...

Page 4

... PLH t PHL PHL t PLH Waveform 3. Propagation delay for set and reset to output, SF00049 INPUT OUTPUT V M OUTPUT N same part SF00051 4 Product specification 74ABT74 PHL PLH SF00050 set and reset pulse width ...

Page 5

... Load capacitance includes jig and probe capacitance; L see AC CHARACTERISTICS for value Termination resistance should be equal pulse generators. 1995 Sep 22 90% NEGATIVE V PULSE POSITIVE V PULSE 10% FAMILY Amplitude of OUT 3.0V 74ABT 5 Product specification 74ABT74 t W AMP (V) 90 10% 10 THL F TLH TLH ...

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