CD4027BCN Fairchild Semiconductor, CD4027BCN Datasheet
CD4027BCN
Manufacturer Part Number
CD4027BCN
Description
IC F/F DUAL JK W/SET&RESET 16DIP
Manufacturer
Fairchild Semiconductor
Series
4000Br
Type
JK Typer
Datasheet
1.CD4027BCN.pdf
(6 pages)
Specifications of CD4027BCN
Function
Set(Preset) and Reset
Output Type
Differential
Number Of Elements
2
Number Of Bits Per Element
1
Frequency - Clock
15.5MHz
Delay Time - Propagation
65ns
Trigger Type
Positive Edge
Current - Output High, Low
8.8mA, 8.8mA
Voltage - Supply
3 V ~ 15 V
Operating Temperature
-55°C ~ 125°C
Mounting Type
Through Hole
Package / Case
16-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
4027
4027B
CD4027
MM5627BN
4027B
CD4027
MM5627BN
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CD4027BCN
Manufacturer:
NS/国半
Quantity:
20 000
© 2004 Fairchild Semiconductor Corporation
CD4027BCM
CD4027BCN
CD4027BC
Dual J-K Master/Slave Flip-Flop with Set and Reset
General Description
The CD4027BC dual J-K flip-flops are monolithic comple-
mentary MOS (CMOS) integrated circuits constructed with
N- and P-channel enhancement mode transistors. Each
flip-flop has independent J, K, set, reset, and clock inputs
and buffered Q and Q outputs. These flip-flops are edge
sensitive to the clock input and change state on the posi-
tive-going transition of the clock pulses. Set or reset is
independent of the clock and is accomplished by a high
level on the respective input.
All inputs are protected against damage due to static dis-
charge by diode clamps to V
Ordering Code:
Connection Diagram
Order Number
Package Number
Top View
M16A
N16E
DD
and V
SS
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
.
DS005958
Features
Truth Table
I
O
X
Note 1: t
transition
Note 2: t
transition
Note 3: Level Change
(Note 3)
HIGH Level
Wide supply voltage range:
High noise immunity: 0.45 V
Low power TTL compatibility: Fan out of 2 driving 74L
or 1 driving 74LS
Low power: 50 nW (typ.)
Medium speed operation: 12 MHz (typ.) with 10V
supply
Don’t Care
LOW Level
CL
LOW-to-HIGH
HIGH-to-LOW
X
X
X
Package Description
n 1
n
refers to the time intervals after the positive clock pulse
refers to the time interval prior to the positive clock pulse
O
J
X
X
X
X
X
X
I
Inputs t
(Note 1)
O
K
X
X
X
X
X
X
I
n 1
O
O
O
O
O
O
S
I
I
R
O
O
O
O
O
O
I
I
October 1987
Revised January 2004
DD
3.0V to 15V
(typ.)
Q
O
O
X
X
X
X
I
I
www.fairchildsemi.com
Q
O
O
O
I
I
I
I
Outputs t
(Note 2)
(No Change)
Q
O
O
O
I
I
I
I
n
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Datasheet:
CD4027BCN Summary of contents
Page 1
... SS Ordering Code: Order Number Package Number CD4027BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow CD4027BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Connection Diagram Top View © 2004 Fairchild Semiconductor Corporation Features Wide supply voltage range: High noise immunity: 0 ...
Page 2
Logic Diagram www.fairchildsemi.com 2 ...
Page 3
Absolute Maximum Ratings (Note 5) DC Supply Voltage ( Input Voltage ( Storage Temperature Range ( Power Dissipation ( Dual-In-Line Small Outline Lead Temperature ( ...
Page 4
AC Electrical Characteristics pF ns, unless otherwise specified A L rCL fCL Symbol Parameter Propagation Delay Time PHL PLH from Clock Propagation ...
Page 5
Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A 5 www.fairchildsemi.com ...
Page 6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...