dm74als109a Fairchild Semiconductor, dm74als109a Datasheet

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dm74als109a

Manufacturer Part Number
dm74als109a
Description
Dual J-k Positive-edge-triggered Flip-flop
Manufacturer
Fairchild Semiconductor
Datasheet

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Part Number:
dm74als109aM
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Quantity:
20 000
© 2000 Fairchild Semiconductor Corporation
DM74ALS109AM
DM74ALS109AN
DM74ALS109A
Dual J-K Positive-Edge-Triggered Flip-Flop
with Preset and Clear
General Description
The DM74ALS109A is a dual edge-triggered flip-flop. Each
flip-flop has individual J, K, clock, clear and preset inputs,
and also complementary Q and Q outputs.
Information at input J or K is transferred to the Q output on
the positive going edge of the clock pulse. Clock triggering
occurs at a voltage level of the clock pulse and is not
directly related to the transition time of the positive going
pulse. When the clock input is at either the HIGH or LOW
level, the J, K input signal has no effect.
Asynchronous preset and clear inputs will set or clear Q
output respectively upon the application of low level signal.
The J-K design allows operation as a D flip-flop by tying the
J and K inputs together.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Order Number
Package Number
M16A
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DS006196
Features
Function Table
L
H
X
Q
Note 1: This condition is nonstable; it will not persist when present and
clear inputs return to their inactive (HIGH) level. The output levels in this
condition are not guaranteed to meet the V
0
Switching specifications at 50 pF
Switching specifications guaranteed over full tempera-
ture and V
Advanced oxide-isolated, ion-implanted Schottky TTL
process
Functionally and pin for pin compatible with Schottky
and LS TTL counterpart
Improved AC performance over LS109 at approximately
half the power
PR
LOW State
Positive Edge Transition,
Don't Care
HIGH State
H
H
H
H
H
H
L
L
Previous Condition of Q
Package Description
CLR
H
H
H
H
H
H
L
L
CC
Inputs
CK
range
X
X
X
L
H
H
J
X
X
X
L
L
X
K
H
H
X
X
X
L
L
X
April 1984
Revised February 2000
OH
H (Note 1)
specification.
Q
Q
Q
H
H
L
L
www.fairchildsemi.com
0
0
TOGGLE
Outputs
H (Note 1)
Q
Q
Q
H
H
L
L
0
0

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dm74als109a Summary of contents

Page 1

... DM74ALS109A Dual J-K Positive-Edge-Triggered Flip-Flop with Preset and Clear General Description The DM74ALS109A is a dual edge-triggered flip-flop. Each flip-flop has individual J, K, clock, clear and preset inputs, and also complementary Q and Q outputs. Information at input transferred to the Q output on the positive going edge of the clock pulse. Clock triggering ...

Page 2

Logic Diagram www.fairchildsemi.com 2 ...

Page 3

Absolute Maximum Ratings Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Typical JA N Package M Package Recommended Operating Conditions Symbol Parameter V Supply Voltage CC V HIGH Level Input Voltage IH V LOW Level Input ...

Page 4

Electrical Characteristics over recommended operating free-air temperature range. All typical values are measured at V Symbol Parameter V Input Clamp Voltage HIGH Level I OH Output Voltage V V LOW Level V OL Output Voltage V I ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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