dm74ls164m Fairchild Semiconductor, dm74ls164m Datasheet

dm74ls164m

Manufacturer Part Number

dm74ls164m

Description

8-bit Serial In/parallel Out Shift Register

Manufacturer

Fairchild Semiconductor

Datasheet

1.DM74LS164M.pdf (5 pages)

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DM74LS164M

DM74LS164N

DM74LS164

8-Bit Serial In/Parallel Out Shift Register

General Description

These 8-bit shift registers feature gated serial inputs and

an asynchronous clear. A low logic level at either input

inhibits entry of the new data, and resets the first flip-flop to

the low level at the next clock pulse, thus providing com-

plete control over incoming data. A high logic level on

either input enables the other input, which will then deter-

mine the state of the first flip-flop. Data at the serial inputs

may be changed while the clock is HIGH or LOW, but only

information meeting the setup and hold time requirements

will be entered. Clocking occurs on the LOW-to-HIGH level

transition of the clock input. All inputs are diode-clamped to

minimize transmission-line effects.

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Order Number

Package Number

M14A

N14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

DS006398

Features

Function Table

indicated steady-state input conditions were established.

clock; indicates a one-bit shift.

Gated (enable/disable) serial inputs

Fully buffered clock and serial inputs

Asynchronous clear

Typical clock frequency 36 MHz

Typical power dissipation 80 mW

Clear

LOW Level (steady state)

Transition from LOW-to-HIGH level

Don't Care (any input, including transitions)

, Q

HIGH Level (steady state)

, Q

Package Description

The level of Q

Clock

Inputs

The level of Q

or Q

, Q

before the most recent

, or Q

August 1986

Revised April 2000

, respectively, before the

www.fairchildsemi.com

Outputs

transition of the

...

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dm74ls164m Summary of contents

Page 1

... All inputs are diode-clamped to minimize transmission-line effects. Ordering Code: Order Number Package Number DM74LS164M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow DM74LS164N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “ ...

Page 2

Logic Diagram Timing Diagram www.fairchildsemi.com 2 ...

Page 3

Absolute Maximum Ratings Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Recommended Operating Conditions Symbol Parameter V Supply Voltage CC V HIGH Level Input Voltage IH V LOW Level Input Voltage IL I HIGH Level Output ...

Page 4

Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow www.fairchildsemi.com Package Number M14A 4 ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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