dm74ls373 Fairchild Semiconductor, dm74ls373 Datasheet

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dm74ls373

Manufacturer Part Number
dm74ls373
Description
3-state Octal D-type Transparent Latches And Edge-triggered Flip-flops
Manufacturer
Fairchild Semiconductor
Datasheet

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© 2000 Fairchild Semiconductor Corporation
DM74LS373WM
DM74LS373SJ
DM74LS373N
DM74LS374WM
DM74LS374SJ
IDM29901NC
DM74LS373 • DM74LS374
3-STATE Octal D-Type Transparent Latches
and Edge-Triggered Flip-Flops
General Description
These 8-bit registers feature totem-pole 3-STATE outputs
designed specifically for driving highly-capacitive or rela-
tively low-impedance loads. The high-impedance state and
increased high-logic level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without need for inter-
face or pull-up components. They are particularly attractive
for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
The eight latches of the DM74LS373 are transparent D-
type latches meaning that while the enable (G) is HIGH the
Q outputs will follow the data (D) inputs. When the enable
is taken LOW the output will be latched at the level of the
data that was set up.
The eight flip-flops of the DM74LS374 are edge-triggered
D-type flip flops. On the positive transition of the clock, the
Q outputs will be set to the logic states that were set up at
the D inputs.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (HIGH or LOW
logic levels) or a high-impedance state. In the high-imped-
ance state the outputs neither load nor drive the bus lines
significantly.
The output control does not affect the internal operation of
the latches or flip-flops. That is, the old data can be
retained or new data can be entered even while the outputs
are OFF.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Order Number
Package Number
M20B
M20D
M20B
M20D
N20A
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DS006431
Features
Choice of 8 latches or 8 D-type flip-flops in a single
package
3-STATE bus-driving outputs
Full parallel-access for loading
Buffered control inputs
P-N-P inputs reduce D-C loading on data lines
Package Description
April 1986
Revised March 2000
www.fairchildsemi.com

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dm74ls373 Summary of contents

Page 1

... They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the DM74LS373 are transparent D- type latches meaning that while the enable (G) is HIGH the Q outputs will follow the data (D) inputs. When the enable is taken LOW the output will be latched at the level of the data that was set up ...

Page 2

... HIGH Level (Steady State) L LOW Level (Steady State) Transition from LOW-to-HIGH level Q The level of the output before steady-state input conditions were established. 0 Logic Diagrams DM74LS373 Transparent Latches www.fairchildsemi.com DM74LS374 DM74LS374 Output Output Clock Control ...

Page 3

... Absolute Maximum Ratings Supply Voltage Input Voltage Storage Temperature Range Operating Free Air Temperature Range DM74LS373 Recommended Operating Conditions Symbol Parameter V Supply Voltage CC V HIGH Level Input Voltage IH V LOW Level Input Voltage IL I HIGH Level Output Current OH I LOW Level Output Current ...

Page 4

... DM74LS373 Switching Characteristics and Symbol Parameter t Propagation Delay Time PLH LOW-to-HIGH Level Output t Propagation Delay Time PHL HIGH-to-LOW Level Output t Propagation Delay Time PLH LOW-to-HIGH Level Output t Propagation Delay Time PHL HIGH-to-LOW Level Output ...

Page 5

DM74LS374 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter V Input Clamp Voltage I V HIGH Level OH Output Voltage V LOW Level OL Output Voltage I Input Current @ Max Input Voltage I ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide www.fairchildsemi.com Package Number M20B 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 7 www.fairchildsemi.com ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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