dm74ls390 Fairchild Semiconductor, dm74ls390 Datasheet
dm74ls390
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dm74ls390 Summary of contents
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... When connected as a bi-qui- nary counter, the separate divide-by-two circuit can be used to provide symmetry (a square wave) at the final out- put stage. The DM74LS390 has parallel outputs from each counter stage so that any submultiple of the input count fre- quency is available for system-timing signals. ...
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Function Tables BCD Count Sequence (Each Counter) (Note 1) Outputs Count ...
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Absolute Maximum Ratings Supply Voltage Input Voltage Clear Operating Free Air Temperature Range Storage Temperature Range Recommended Operating Conditions Symbol Parameter V Supply Voltage CC V HIGH Level Input Voltage IH V LOW Level Input Voltage IL ...
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Switching Characteristics and Symbol Parameter f Maximum Clock MAX Frequency t Propagation Delay Time PLH LOW-to-HIGH Level Output t Propagation Delay Time PHL HIGH-to-LOW Level Output t Propagation Delay Time PLH LOW-to-HIGH ...
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Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A 5 www.fairchildsemi.com ...
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Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said ...