dm74ls393 Fairchild Semiconductor, dm74ls393 Datasheet

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dm74ls393

Manufacturer Part Number
dm74ls393
Description
Dual 4-bit Binary Counter
Manufacturer
Fairchild Semiconductor
Datasheet

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Part Number:
DM74LS393
Manufacturer:
FSC
Quantity:
450
© 2000 Fairchild Semiconductor Corporation
DM74LS393M
DM74LS373N
DM74LS393
Dual 4-Bit Binary Counter
General Description
Each of these monolithic circuits contains eight master-
slave flip-flops and additional gating to implement two indi-
vidual four-bit counters in a single package. The
DM74LS393 comprises two independent four-bit binary
counters each having a clear and a clock input. N-bit binary
counters can be implemented with each package providing
the capability of divide-by-256. The DM74LS393 has paral-
lel outputs from each counter stage so that any submultiple
of the input count frequency is available for system-timing
signals.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Order Number
Package Number
M14A
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DS006434
Features
Function Table
H
L
Dual version of the popular DM74LS93
DM74LS393 dual 4-bit binary counter with individual
clocks
Direct clear for each 4-bit counter
Dual 4-bit versions can significantly improve system
densities by reducing counter package count by 50%
Typical maximum count frequency 35 MHz
Buffered outputs reduce possibility of collector commu-
tation
LOW Logic Level
HIGH Logic Level
Package Description
Count
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
Counter Sequence (Each Counter)
Q
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
D
Q
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
August 1986
Revised March 2000
C
Outputs
Q
www.fairchildsemi.com
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
B
Q
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
A

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dm74ls393 Summary of contents

Page 1

... DM74LS393 comprises two independent four-bit binary counters each having a clear and a clock input. N-bit binary counters can be implemented with each package providing the capability of divide-by-256. The DM74LS393 has paral- lel outputs from each counter stage so that any submultiple of the input count frequency is available for system-timing signals ...

Page 2

Logic Diagram www.fairchildsemi.com 2 ...

Page 3

Absolute Maximum Ratings Supply Voltage Input Voltage Clear A Operating Free Air Temperature Range Storage Temperature Range Recommended Operating Conditions Symbol Parameter V Supply Voltage CC V HIGH Level Input Voltage IH V LOW Level Input Voltage IL I HIGH ...

Page 4

Switching Characteristics and Symbol Parameter f Maximum Clock Frequency MAX t Propagation Delay Time PLH LOW-to-HIGH Level Output t Propagation Delay Time PHL HIGH-to-LOW Level Output t Propagation Delay Time PLH LOW-to-HIGH ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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