74aup1g58gw NXP Semiconductors, 74aup1g58gw Datasheet

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74aup1g58gw

Manufacturer Part Number
74aup1g58gw
Description
74aup1g58 Low-power Configurable Multiple Function Gate
Manufacturer
NXP Semiconductors
Datasheet

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Part Number
Manufacturer
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Price
Part Number:
74AUP1G58GW
Manufacturer:
NXP/恩智浦
Quantity:
20 000
1. General description
2. Features
The 74AUP1G58 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
This device ensures a very low static and dynamic power consumption across the entire
V
This device is fully specified for partial power-down applications using I
The I
the device when it is powered down.
The 74AUP1G58 provides configurable multiple functions. The output state is determined
by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,
NOR, XOR, inverter and buffer. All inputs can be connected to V
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
The inputs switch at different points for positive and negative-going signals. The difference
between the positive voltage V
hysteresis voltage V
I
I
I
I
I
I
I
I
I
I
CC
74AUP1G58
Low-power configurable multiple function gate
Rev. 01 — 31 January 2007
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
ESD protection:
Low static-power consumption; I
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
I
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
OFF
N
N
N
range from 0.8 V to 3.6 V.
OFF
HBM JESD22-A114D Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
circuitry provides partial Power-down mode operation
circuitry disables the output, preventing the damaging backflow current through
H
.
CC
range from 0.8 V to 3.6 V.
T+
and the negative voltage V
CC
= 0.9 A (maximum)
CC
T
is defined as the input
CC
Product data sheet
or GND.
OFF
.

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74aup1g58gw Summary of contents

Page 1

Low-power configurable multiple function gate Rev. 01 — 31 January 2007 1. General description The 74AUP1G58 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. This device ensures a very low static ...

Page 2

... Temperature range Name 74AUP1G58GW +125 C 74AUP1G58GM +125 C 74AUP1G58GF +125 C 4. Marking Table 2. Marking Type number 74AUP1G58GW 74AUP1G58GM 74AUP1G58GF 5. Functional diagram Fig 1. Logic symbol 74AUP1G58_1 Product data sheet Low-power configurable multiple function gate Description SC-88 plastic surface-mounted package; 6 leads XSON6 plastic extremely thin small outline package ...

Page 3

... NXP Semiconductors 6. Pinning information 6.1 Pinning 74AUP1G58 GND 001aad697 Fig 2. Pin configuration SOT363 (SC-88) 6.2 Pin description Table 3. Pin description Symbol Pin B 1 GND Functional description [1] Table 4. Function table Input ...

Page 4

... NXP Semiconductors 7.1 Logic configurations Table 5. Function selection table Logic function 2-input NAND 2-input NAND with both inputs inverted 2-input AND with inverted input 2-input NOR with inverted input 2-input OR 2-input OR with both inputs inverted 2-input XOR Buffer Inverter ...

Page 5

... NXP Semiconductors Fig 11. Inverter 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current IK V input voltage I I output clamping current OK V output voltage ...

Page 6

... NXP Semiconductors 10. Static characteristics Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter amb V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current I I power-off leakage current OFF I additional power-off leakage OFF current ...

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... NXP Semiconductors Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter V LOW-level output voltage OL I input leakage current I I power-off leakage current OFF I additional power-off leakage OFF current I supply current CC I additional supply current +125 C ...

Page 8

... NXP Semiconductors Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter I additional power-off leakage OFF current I supply current CC I additional supply current CC 11. Dynamic characteristics Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see ...

Page 9

... NXP Semiconductors Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions propagation delay A, B and see pF and power dissipation MHz capacitance [1] All typical values are measured at nominal V ...

Page 10

... NXP Semiconductors 12. Waveforms input Measurement points are given in V and V are typical output voltage drops that occur with the output load Fig 12. Input A, B and C to output Y propagation delay times Table 10. Measurement points Supply voltage 3.6 V Test data is given in Table 11 ...

Page 11

... NXP Semiconductors Table 11. Test data Supply voltage Input [1] For measuring enable and disable times 13. Transfer characteristics Table 12. Transfer characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter ...

Page 12

... NXP Semiconductors 14. Waveforms transfer characteristics Fig 14. Transfer characteristic 240 160 0.4 0.8 Fig 16. Typical transfer characteristics; V 74AUP1G58_1 Product data sheet V I mna207 Fig 15. Definition of V 001aad691 ( A) 1.2 1.6 2 1.8 V Fig 17. Typical transfer characteristics Rev. 01 — 31 January 2007 74AUP1G58 Low-power confi ...

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... NXP Semiconductors 15. Package outline Plastic surface-mounted package; 6 leads y 6 pin 1 index DIMENSIONS (mm are the original dimensions UNIT max 0.30 1.1 0.25 mm 0.1 0.20 0.8 0.10 OUTLINE VERSION IEC SOT363 Fig 18. Package outline SOT363 (SC-88) 74AUP1G58_1 Product data sheet scale ...

Page 14

... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1. (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 1.5 mm 0.5 0.04 0.17 1.4 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION ...

Page 15

... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 0 terminal 1 index area DIMENSIONS (mm are the original dimensions UNIT b D max max 0.20 1.05 mm 0.5 0.04 0.12 0.95 OUTLINE VERSION IEC SOT891 Fig 20. Package outline SOT891 (XSON6) 74AUP1G58_1 Product data sheet ...

Page 16

... NXP Semiconductors 16. Abbreviations Table 13. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 17. Revision history Table 14. Revision history Document ID Release date 74AUP1G58_1 ...

Page 17

... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...

Page 18

... NXP Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 3 7.1 Logic configurations . . . . . . . . . . . . . . . . . . . . . 4 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 12 Waveforms ...

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