74cbtlv3245bq NXP Semiconductors, 74cbtlv3245bq Datasheet

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74cbtlv3245bq

Manufacturer Part Number
74cbtlv3245bq
Description
74cbtlv3245 8-bit Bus Switch With Output Enable
Manufacturer
NXP Semiconductors
Datasheet

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Part Number:
74cbtlv3245bq-Q10X
Manufacturer:
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Quantity:
20 000
Part Number:
74cbtlv3245bq115
Manufacturer:
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1. General description
2. Features and benefits
The 74CBTLV3245 is an 8-pole, single-throw bus switch. The device features a single
output enable input (OE) that controls eight switch channels. The switches are disabled
when OE is HIGH. Schmitt-trigger action at control inputs makes the circuit tolerant of
slower input rise and fall times. This device is fully specified for partial power-down
applications using I
backflow current through the device when it is powered down.
74CBTLV3245
8-bit bus switch with output enable
Rev. 1 — 30 December 2010
Supply voltage range from 2.3 V to 3.6 V
High noise immunity
Complies with JEDEC standard:
ESD protection:
5  switch connection between two ports
Rail to rail switching on data I/O ports
CMOS low power consumption
Latch-up performance exceeds 250 mA per JESD78B Class I level A
I
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
OFF
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM AEC-Q100-011 revision B exceeds 1000 V
circuitry provides partial Power-down mode operation
OFF
. The I
OFF
circuitry disables the output, preventing the damaging
Product data sheet

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74cbtlv3245bq Summary of contents

Page 1

Rev. 1 — 30 December 2010 1. General description The 74CBTLV3245 is an 8-pole, single-throw bus switch. The device features a single output enable input (OE) that controls eight switch channels. The switches ...

Page 2

... Table 1. Ordering information Type number Package Temperature range 40 C to +125 C SSOP20 74CBTLV3245DS 74CBTLV3245PW 40 C to +125 C TSSOP20 40 C to +125 C DHVQFN20 74CBTLV3245BQ [1] Also known as QSOP20 package 4. Functional diagram 19 OE Fig 1. Logic symbol Fig 2. Logic diagram (one switch) ...

Page 3

... NXP Semiconductors 5. Pinning information 5.1 Pinning 74CBTLV3245 n. GND 10 Fig 3. Pin configuration for TSSOP20 (SOT360-1) (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However soldered, the solder land should remain floating or be connected to GND ...

Page 4

... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol Pin GND 18, 17, 16, 15, 14, 13, 12 Functional description [1] Table 3. Function selection Input [ HIGH voltage level LOW voltage level high-impedance OFF-state. ...

Page 5

... NXP Semiconductors 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V switch voltage SW T ambient temperature amb t/V input transition rise and fall rate [1] Applies to control signal levels. 9. Static characteristics Table 6. Static characteristics At recommended operating conditions voltages are referenced to GND (ground = 0 V). ...

Page 6

... NXP Semiconductors 9.1 Test circuits GND GND and V = GND Fig 6. Test circuit for measuring OFF-state leakage current (one switch) 9.2 ON resistance Table 7. Resistance recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see ...

Page 7

... NXP Semiconductors 9.3 ON resistance test circuit and graphs GND Fig 8. Test circuit for measuring ON resistance (one switch (Ω (1) (2) 5 (3) ( 0.5 1.0 = 125 C. (1) T amb = 85 C. (2) T amb = 25 C. (3) T amb = 40 C. ...

Page 8

... NXP Semiconductors (Ω) 6 (1) (2) ( 125 C. (1) T amb = 85 C. (2) T amb = 25 C. (3) T amb = 40 C. (4) T amb Fig 12. ON resistance as a function of input voltage 3 125 C. (1) T amb = 85 C. (2) T amb = 25 C. ...

Page 9

... NXP Semiconductors 10. Dynamic characteristics Table 8. Dynamic characteristics GND = 0 V; for test circuit see Figure 17 Symbol Parameter Conditions t propagation delay An; pd see enable time Bn; en see disable time Bn; dis see V V [1] All typical values are measured at T ...

Page 10

... NXP Semiconductors OE input output LOW to OFF OFF to LOW output HIGH to OFF OFF to HIGH Measurement points are given in Logic levels: V and Fig 16. Enable and disable times 74CBTLV3245 Product data sheet GND t PLZ PHZ GND ...

Page 11

... NXP Semiconductors Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to the output impedance External voltage for measuring switching times. EXT Fig 17. Test circuit for measuring switching times Table 10 ...

Page 12

... NXP Semiconductors 12. Package outline SSOP20: plastic shrink small outline package; 20 leads; body width 3.9 mm; lead pitch 0.635 DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) A UNIT max. 0.25 1.55 mm 1.73 0.25 0.10 1.40 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. ...

Page 13

... NXP Semiconductors TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 14

... NXP Semiconductors DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 15

... NXP Semiconductors 13. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 14. Revision history Table 12. Revision history Document ID Release date 74CBTLV3245 v.1 20101230 74CBTLV3245 Product data sheet ...

Page 16

... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

Page 17

... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16. Contact information For more information, please visit: For sales office addresses, please send an email to: 74CBTLV3245 Product data sheet 15 ...

Page 18

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics 9.1 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 9.2 ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 6 9.3 ON resistance test circuit and graphs Dynamic characteristics ...

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