74cbtlv3384bq NXP Semiconductors, 74cbtlv3384bq Datasheet

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74cbtlv3384bq

Manufacturer Part Number
74cbtlv3384bq
Description
74cbtlv3384 10-bit Bus Switch With 5-bit Output Enables
Manufacturer
NXP Semiconductors
Datasheet
1. General description
2. Features and benefits
The 74CBTLV3384 is a dual 5-pole, single-throw bus switch. The device features two
output enable inputs (nOE) that each control five switch channels. The switches are
disabled when the associated nOE input is HIGH. Schmitt-trigger action at control inputs
makes the circuit tolerant of slower input rise and fall times. This device is fully specified
for partial power-down applications using I
preventing the damaging backflow current through the device when it is powered down.
74CBTLV3384
10-bit bus switch with 5-bit output enables
Rev. 1 — 30 December 2010
Supply voltage range from 2.3 V to 3.6 V
High noise immunity
Complies with JEDEC standard:
ESD protection:
5  switch connection between two ports
Rail to rail switching on data I/O ports
CMOS low power consumption
Latch-up performance exceeds 250 mA per JESD78B Class I level A
I
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
OFF
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM AEC-Q100-011 revision B exceeds 1000 V
circuitry provides partial Power-down mode operation
OFF
. The I
OFF
circuitry disables the output,
Product data sheet

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74cbtlv3384bq Summary of contents

Page 1

Rev. 1 — 30 December 2010 1. General description The 74CBTLV3384 is a dual 5-pole, single-throw bus switch. The device features two output enable inputs (nOE) that each control five switch channels. ...

Page 2

... Ordering information Type number Package Temperature range 40 C to +125 C SSOP24 74CBTLV3384DK 74CBTLV3384PW 40 C to +125 C TSSOP24 40 C to +125 C DHVQFN24 74CBTLV3384BQ [1] Also known as QSOP24 package 4. Functional diagram Fig 1. Logic symbol Fig 2. Logic diagram (one switch) 74CBTLV3384 Product data sheet ...

Page 3

... NXP Semiconductors 5. Pinning information 5.1 Pinning 74CBTLV3384 1OE 1 1B1 2 3 1A1 4 1A2 1B2 5 1B3 6 1A3 7 8 1A4 9 1B4 1B5 10 1A5 11 GND 12 Fig 3. Pin configuration for TSSOP24 (SOT355-1) (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad ...

Page 4

... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol Pin 1OE, 2OE 1, 13 1A1 to 1A5 2A1 to 2A5 14, 17, 18, 21, 22 1B1 to 1B5 2B1 to 2B5 15, 16, 19, 20, 23 GND Functional description [1] Table 3. Function selection Input 1OE 2OE ...

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... NXP Semiconductors 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V switch voltage SW T ambient temperature amb t/V input transition rise and fall rate [1] Applies to control signal levels. 9. Static characteristics Table 6. Static characteristics At recommended operating conditions voltages are referenced to GND (ground = 0 V). ...

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... NXP Semiconductors 9.1 Test circuits V CC nOE nBn A GND GND and V = GND Fig 6. Test circuit for measuring OFF-state leakage current (one switch) 9.2 ON resistance Table 7. Resistance recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see ...

Page 7

... NXP Semiconductors 9.3 ON resistance test circuit and graphs nOE V IL nAn GND Fig 8. Test circuit for measuring ON resistance (one switch (Ω (1) (2) 5 (3) ( 0.5 1.0 = 125 C. (1) T amb = 85 C. (2) T amb = 25 C. (3) T amb =  ...

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... NXP Semiconductors (Ω) 6 (1) (2) ( 125 C. (1) T amb = 85 C. (2) T amb = 25 C. (3) T amb = 40 C. (4) T amb Fig 12. ON resistance as a function of input voltage 3 125 C. (1) T amb = 85 C. (2) T amb = 25 C. ...

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... NXP Semiconductors 10. Dynamic characteristics Table 8. Dynamic characteristics GND = 0 V; for test circuit see Figure 17 Symbol Parameter Conditions t propagation delay nAn to nBn or nBn to pd nAn; see enable time nOE to nAn or nBn; en see disable time nOE to nAn or nBn; dis see V V [1] ...

Page 10

... NXP Semiconductors nOE input output LOW to OFF OFF to LOW output HIGH to OFF OFF to HIGH Measurement points are given in Logic levels: V and Fig 16. Enable and disable times 74CBTLV3384 Product data sheet GND t PLZ PHZ GND ...

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... NXP Semiconductors Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to the output impedance External voltage for measuring switching times. EXT Fig 17. Test circuit for measuring switching times Table 10 ...

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... NXP Semiconductors 12. Package outline SSOP24: plastic shrink small outline package; 24 leads; body width 3.9 mm; lead pitch 0.635 DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) A UNIT max. 0.25 1.55 mm 1.73 0.25 0.10 1.40 0.0098 0.061 inches 0.068 0.01 0.0040 0.055 Note 1 ...

Page 13

... NXP Semiconductors TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 14

... NXP Semiconductors DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 15

... NXP Semiconductors 13. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 12. Revision history Document ID Release date 74CBTLV3384 v.1 20101230 ...

Page 16

... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

Page 17

... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16. Contact information For more information, please visit: For sales office addresses, please send an email to: 74CBTLV3384 Product data sheet 15 ...

Page 18

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics 9.1 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 9.2 ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 6 9.3 ON resistance test circuit and graphs Dynamic characteristics ...

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