fxl2sd106 Fairchild Semiconductor, fxl2sd106 Datasheet

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fxl2sd106

Manufacturer Part Number
fxl2sd106
Description
Low Voltage Dual Supply 6-bit Sd Interface Voltage Translator With Configurable Voltage Supplies And Signal Levels, 3-state Outputs, And Auto Direction Sensing
Manufacturer
Fairchild Semiconductor
Datasheet

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©2008 Fairchild Semiconductor Corporation
FXL2SD106 Rev. 1.8.0
FXL2SD106
Low Voltage Dual Supply 6-Bit SD Interface Voltage
Translator with Configurable Voltage Supplies and Signal
Levels, 3-State Outputs, and Auto Direction Sensing
Features
Ordering Information
Bi-directional interface between two levels from 1.1V
to 3.6V
Fully configurable: Inputs and outputs track V
Non-preferential power-up; either VCC may be
powered-up first
Outputs remain in 3-state until active V
reached
Outputs switch to 3-state if either V
Power off protection
Bushold on data inputs eliminates the need for SDIO
pull-up resistors
Control input (OE and CLK IN) are referenced to V
voltage
Packaged in 16-terminal DQFN (2.5mm x 3.5mm)
Direction control not needed
80 Mbps throughput when translating between 1.8V
and 2.5V
ESD protection exceeds:
– 12kV HBM (B port I/O to GND)
– 8kV HBM (A port I/O to GND)
– 1kV CDM (per ESD STM 5.3)
Order Number
FXL2SD106BQX
All packages are lead free per JEDEC: J-STD-020B standard.
(per JESD22-A114 & Mil Std 883e 3015.7)
(per JESD22-A114 & Mil Std 883e 3015.7)
Package Number
MLP16E
CC
is at GND.
CC
level is
CC
level
CCA
16-Terminal Depopulated Quad Very-Thin Flat Pack,
No Leads (DQFN), JEDEC MO-241, 2.5mm x 3.5mm
General Description
The FXL2SD106 is a configurable dual-voltage-supply
translator designed for both uni-directional and bi-
directional voltage translation between two logic levels.
The device allows translation between voltages as high
as 3.6V to as low as 1.1V. The A port tracks the V
level, and the B port tracks the V
for bi-directional voltage translation over a variety of volt-
age levels: 1.2V, 1.5V, 1.8V, 2.5V and 3.3V.
The FXL2SD106 is specifically designed as a translator
to interface with the SDIO standard. I/O capacitance is
managed to meet the SD maximum capacitance specifi-
cation. The B side ESD performance allows interface as
an external card and the part can handle 80 Mbps
throughput when translating between 1.8V and 2.5V.
The device remains in 3-state until both V
active levels allowing either V
Internal power down control circuits place the device in
3-state if either VCC is removed.
The OE input, when low, disables both the A and B ports
by placing them in a 3-state condition. The FXL2SD106
is designed so that both control pins (OE and CLK IN)
are supplied by V
The device senses an input signal on A or B port
automatically. The input signal is transferred to the other
port.
Package Description
CCA
.
CC
to be powered-up first.
CCB
level. This allows
www.fairchildsemi.com
June 2008
CC
s reach
CCA

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fxl2sd106 Summary of contents

Page 1

... Internal power down control circuits place the device in 3-state if either VCC is removed. The OE input, when low, disables both the A and B ports by placing them in a 3-state condition. The FXL2SD106 is designed so that both control pins (OE and CLK IN) are supplied by V The device senses an input signal port automatically ...

Page 2

... GND 10–13 B –B B Side Inputs or 3-State 3 0 Outputs 14 CMD B 15 CLK OUT 3-State Output Side Power Supply CCB ©2008 Fairchild Semiconductor Corporation FXL2SD106 Rev. 1.8.0 Functional Diagram OE CLK OUT CMD B CMD – CLK IN Function Table Description ...

Page 3

... Static Output Current I T Free Air Operating Temperature Maximum Input Edge Rate V Note: 2. All unused inputs and I/O pins must be held at V ©2008 Fairchild Semiconductor Corporation FXL2SD106 Rev. 1.8.0 Parameter (1) , CMD CMD B, CLK OUT (2) Parameter /I with V ...

Page 4

... OZ Leakage (7)(8) I Quiescent 1.1–3.6 CCA/B Supply Current (7) I Quiescent 1.1–3.6 CCZ Supply Current ©2008 Fairchild Semiconductor Corporation FXL2SD106 Rev. 1.8 –40°C to +85°C) A (V) V (V) Conditions CCB 1.1–3.6 Data inputs An, CMD A, Control inputs CLK IN, OE 1.1–3.6 1.4–3.6 Data inputs Bn, CMD B 1.1–1.4 1.1–3.6 ...

Page 5

... OHD Current High (11) I Dynamic Output +18.0 OLD Current Low Notes: 9. Dynamic Output Characteristics are guaranteed but not tested. 10. See Figure 5. 11. See Figure 6. ©2008 Fairchild Semiconductor Corporation FXL2SD106 Rev. 1.8 –40°C to +85°C) (Continued) A (V) V (V) Conditions CCB 0 1.1–3 GND; I ...

Page 6

... Skew is the variation of propagation delay between output signals and applies only to output signals on the same port (An, CMD A or Bn, CMD B) and switching with the same polarity (Low-to-High or High-to-Low). See Figure 8. ©2008 Fairchild Semiconductor Corporation FXL2SD106 Rev. 1.8 -40°C to +85° 3.0V– ...

Page 7

... For example, 100 Mbps is equivalent to 50 MHz. Capacitance Symbol Cin Input Capacitance, Control pin (OE, CLK IN) Ci/o Input/Output Capacitance Cpd Power Dissipation Capacitance ©2008 Fairchild Semiconductor Corporation FXL2SD106 Rev. 1.8 -40°C to +85° Min. Min. 100 80 100 ...

Page 8

... AC Load Table ©2008 Fairchild Semiconductor Corporation FXL2SD106 Rev. 1.8 TEST DUT SIGNAL C1 Output Enable Test Input Signal Data Pulses PLH PHL t 0V Low to High Switch PZL t V Low to High Switch PZH CCI Figure 1. AC Test Circuit V Cl CCO 1.2V ± 0.1V 15pF 1.5V ± ...

Page 9

... DATA V x OUT Input 2.0ns, 10 Input 2.5ns, 10 3.0V to 3.6V only R F Figure 4. 3-STATE Output High Enable Time for Low Voltage Logic ©2008 Fairchild Semiconductor Corporation FXL2SD106 Rev. 1.8.0 V CCI V mi OUTPUT GND CONTROL t pxx V CCO V DATA mo OUT Input t ...

Page 10

... Figure 5. Active Output Rise Time and Dynamic Output Current High t W DATA V /2 CCI IN Max. data rate 1/t W Figure 7. Maximum Data Rate ©2008 Fairchild Semiconductor Corporation FXL2SD106 Rev. 1.8 80 CCO V OUT CCO (20% – 80 CCO ) I/O OLD t RISE Figure 6. Active Output Fall Time and Dynamic ...

Page 11

... Tape and Reel Specification Tape Format for DQFN 10 Package Designator Section BQX Leader (Start End) Trailer (Hub End) Tape Dimensions millimeters ©2008 Fairchild Semiconductor Corporation FXL2SD106 Rev. 1.8.0 Tape Number Cavities 125 (typ) Carrier 2500/3000 75 (typ) 11 Cavity Cover Tape Status Status Empty ...

Page 12

... Reel Dimensions inches (millimeters) Tape Size A 12mm 13.0 (330) ©2008 Fairchild Semiconductor Corporation FXL2SD106 Rev. 1.8 0.059 0.512 0.795 (1.50) (13.00) (20.20 7.008 0.488 0.724 (178) (12.4) (18.4) www.fairchildsemi.com ...

Page 13

... Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©2008 Fairchild Semiconductor Corporation FXL2SD106 Rev. 1.8.0 13 www.fairchildsemi.com ...

Page 14

... Datasheet Identification Product Status Advance Information Formative / In Design Preliminary First Production No Identification Needed Full Production Obsolete Not In Production ©2008 Fairchild Semiconductor Corporation FXL2SD106 Rev. 1.8.0 PDP SPM™ Power-SPM™ ® PowerTrench SM Programmable Active Droop™ ® QFET QS™ Quiet Series™ ...

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