nlsx3012 ON Semiconductor, nlsx3012 Datasheet

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nlsx3012

Manufacturer Part Number
nlsx3012
Description
2-bit 100 Mb/s Configurable Dual-supply Level Translator
Manufacturer
ON Semiconductor
Datasheet

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NLSX3012
2-Bit 100 Mb/s Configurable
Dual-Supply Level
Translator
level translator without a direction control pin. The I/O V
V
and V
to 4.5 V while the V
- 0.4) V. This allows lower voltage logic signals on the V
translated into higher voltage logic signals on the V
vice-versa. Both I/O ports are auto-sensing; thus, no direction pin is
required.
by putting them in 3-state. This significantly reduces the supply
currents from both V
V
Features
Typical Applications
© Semiconductor Components Industries, LLC, 2007
September, 2007 - Rev. 0
L
L
The NLSX3012 is a 2-bit configurable dual-supply bidirectional
The Output Enable (EN) input, when Low, disables both I/O ports
Wide Low-Side V
Wide High-Side V
High-Speed with 140 Mb/s Guaranteed Date Rate for V
Low Bit-to-Bit Skew
Overvoltage Tolerant Enable and I/O Pins
Non-preferential Powerup Sequencing
Small packaging: 1.8 mm x 1.2 mm UDFN8
This is a Pb-Free Device
Mobile Phones, PDAs, Other Portable Devices
PC and Laptops
-ports are designed to track two different power supply rails, V
.
L
respectively. The V
L
CC
L
CC
supply rail is configurable from 0.9 V to (V
Operating Range: 0.9 V to (V
and V
Operating Range: 1.3 V to 4.5 V
CC
supply rail is configurable from 1.3 V
L
. The EN signal is designed to track
CC
CC
- 0.4) V
CC
L
side to be
side, and
L
- and I/O
1
> 1.8 V
CC
CC
I/O V
I/O V
†For information on tape and reel specifications,
NLSX3012MUTAG
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
EN
L
L
1
1
2
Device
I/O V
I/O V
ORDERING INFORMATION
8
VA = Specific Device Code
M
G
GND
V
L
L
http://onsemi.com
PIN ASSIGNMENT
LOGIC DIAGRAM
1
2
L
CASE 517AJ
= Date Code
= Pb-Free Package
MU SUFFIX
1
2
3
4
UDFN8
(Top View)
(Pb-Free)
Package
UDFN8
Publication Order Number:
8
7
6
5
3000/T ape & Reel
V
V
I/O V
I/O V
EN
L
MARKING
DIAGRAM
CC
Shipping
NLSX3012/D
V
VAM
CC
CC
CC
G
I/O V
I/O V
1
2
GND
CC
CC
1
2

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nlsx3012 Summary of contents

Page 1

... NLSX3012 2-Bit 100 Mb/s Configurable Dual-Supply Level Translator The NLSX3012 is a 2-bit configurable dual-supply bidirectional level translator without a direction control pin. The I -ports are designed to track two different power supply rails and V respectively. The V supply rail is configurable from 1 4.5 V while the V supply rail is configurable from 0 ...

Page 2

... V Input Voltage Input Voltage L L GND Ground EN Output Enable I I/O Port, Referenced I I/O Port, Referenced NLSX3012 V L +3.6V CC +3.6 V System I I/O1 2 I/O2 GND Figure 2. Simplified Functional Diagram (1 I/O Line) FUNCTION TABLE http://onsemi.com One-Shot ...

Page 3

... V V Supply Voltage Enable Control Pin Voltage EN V Bus Input/Output Voltage IO T Operating Temperature Range A DI/DV Input Transition Rise or Rate from 30 NLSX3012 -0.5 to +5.5 -0.5 to +5 -0 -65 to +150 Parameter http://onsemi.com 3 Value Condition + 0 ...

Page 4

... the supply voltage associated with the low voltage port during startup and shutdown conditions Typical values are for temperature range are guaranteed by design. NLSX3012 Test Conditions V (V) CC (Note 1) (Note 2) 1.3 to 4.5 0 1.3 to 4.5 0 ...

Page 5

... the supply voltage associated with the low voltage port during startup and shutdown conditions Typical values are for temperature range are guaranteed by design. NLSX3012 Test Conditions V (V) CC (Note 5) (Note 1.3 to 3.6 0 ...

Page 6

... the supply voltage associated with the low voltage port during startup and shutdown conditions, V 12. Typical values are for temperature range are guaranteed by design. NLSX3012 Test Conditions V (V) CC (Note 9) (Note 10 1.3 to 4.5 IOVCC ...

Page 7

... CC 0 – 0.4) 140 160 CC 0 – 0.4) 180 275 CC 0 – 0.4) 160 220 CC – 0.4) V during normal operation. However +25 °C. Limits over the operating A NLSX3012 V EN I IOVL RISE/FALL t PD_VCC- F-VL R-VL Test Circuit and Timing CC Unit ...

Page 8

... Figure 5. Test Circuit for Enable/Disable Time Measurement t R 90% Input 50% 10% t PLH 90% 50% Output 10 Figure 6. Timing Definitions for Propagation Delays and Enable/Disable Measurement NLSX3012 V CC DUT Test Switch Open equivalent of pulse generator (typically 50% ...

Page 9

... NLSX3012 translator options for an application such as the I requires pullup resistors. Enable Input (EN) The NLSX3012 has an Enable pin (EN) that provides tri-state operation at the I/O pins. Driving the Enable pin to a low logic level minimizes the power consumption of ports, input signals the device and drives the I/O V impedance state ...

Page 10

... CONSTRUCTION FOR TERMINALS. MILLIMETERS DIM MIN MAX A 0.45 0.55 A1 0.00 0.05 A3 0.127 REF b 0.15 0.25 b2 0.30 REF D 1.80 BSC E 1.20 BSC e 0.40 BSC L 0.45 0.55 L1 0.00 0.03 L2 0.40 REF MOUNTING FOOTPRINT SOLDERMASK DEFINED 8X 0.66 7X 1.50 1 0.40 PITCH DIMENSIONS: MILLIMETERS ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your loca Sales Representative NLSX3012/D ...

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