nlsx5011 ON Semiconductor, nlsx5011 Datasheet
nlsx5011
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nlsx5011 Summary of contents
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... V side to be translated to either a higher lower logic signal voltage on the V The NLSX5011 offers the feature that the values of the V supplies are independent. Design flexibility is maximized because V can be set to a value either greater than or less than the V L supply ...
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... Figure 2. Simplified Functional Diagram (1 I/O Line) 2 Peripheral EN GPIO ANO < V Figure 4. Application Example for http://onsemi.com One−Shot R1 N One−Shot I One−Shot R2 N One−Shot 1 Peripheral L CC NLSX5011 I I GND > ...
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EN I Figure 5. Logic Diagram PIN ASSIGNMENT Pins Description V V Input Voltage Input Voltage L L GND Ground EN Output Enable I I/O Port, Referenced I/O V ...
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DC ELECTRICAL CHARACTERISTICS Symbol Parameter V I/O V Input HIGH Voltage IHC CC V I/O V Input LOW Voltage ILC CC V I/O V Input HIGH Voltage IHL L V I/O V Input LOW Voltage ILL L V Control Pin ...
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TIMING CHARACTERISTICS Symbol Parameter t I/O V Rise Time R−VCC CC t I/O V Fall Time F−VCC CC t I/O V Rise Time R− I/O V Fall Time F− I/O V One−Shot OVCC CC Output Impedance ...
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TIMING CHARACTERISTICS (continued) Symbol Parameter t I/O_V Output Enable Time EN−VCC CC t I/O_V Output Enable Time EN− I/O_V Output Disable Time DIS−VCC CC t I/O_V Output Disable Time DIS−VL L MDR Maximum Data Rate 10. Normal test ...
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DYNAMIC POWER CONSUMPTION Symbol Parameter Input port MHz, PD_VL L Load V = Output Port Input port MHz, ...
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STATIC POWER CONSUMPTION (T Symbol Parameter Input port MHz, PD_VL L Load V = Output Port EN = GND (outputs disabled Input port ...
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... Test PHZ PLZ = equivalent 1 of pulse generator (typically 50 W) OUT GND t PHL Output t F Output http://onsemi.com 9 NLSX5011 I Source RISE/FALL t PD_VCC− F−VL R−VL Test Circuit and Timing CC 2xV CC OPEN ...
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... CMOS input stage. Enable Input (EN) The NLSX5011 translator has an Enable pin (EN) that provides tri−state operation at the I/O pins. Driving the Enable pin to a low logic level minimizes the power consumption of the device and drives the I pins to a high impedance state ...
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... SEATING PLANE 0.40 PITCH *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0 ...
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... *For additional information on our Pb−Free strategy and soldering 0.05 C NOTE 3 details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 12 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND ...
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... PACKAGE IS ALLOWED. MILLIMETERS DIM MIN MAX −−− 0. 0.00 0.05 b 0.15 0.25 D 1.45 BSC E 1.00 BSC e 0.50 BSC L 0.25 0.35 L1 0.30 0.40 MOUNTING FOOTPRINT SOLDERMASK DEFINED 0.49 0.30 1.24 1 0.50 PKG OUTLINE PITCH DIMENSIONS: MILLIMETERS ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your loca Sales Representative NLSX5011/D ...