24lc32a Microchip Technology Inc., 24lc32a Datasheet - Page 7

• Manufacturer Part Number: 24lc32a
• Description: 32k I2c Serial Eeprom
• Manufacturer: Microchip Technology Inc.

4.0
4.1
Following the Start condition from the master, the
R/W bit (which is a logic low) are clocked onto the bus
by the master transmitter. This indicates to the
addressed slave receiver that the address high byte
will follow once it has generated an Acknowledge bit
during the ninth clock cycle. Therefore, the next byte
transmitted by the master is the high-order byte of the
word address and will be written into the Address
Pointer of the 24XX32A. The next byte is the Least
Significant Address Byte. After receiving another
Acknowledge signal from the 24XX32A, the master
device will transmit the data word to be written into the
addressed memory location. The 24XX32A acknowl-
edges again and the master generates a Stop
during this time, the 24XX32A will not generate
Acknowledge signals (Figure 4-1). If an attempt is
made to write to the array with the WP pin held high,
the device will acknowledge the command, but no
write cycle will occur. No data will be written and the
device will immediately accept a new command. After
a byte Write command, the internal address counter
will point to the address location following the one that
was just written.
© 2007 Microchip Technology Inc.
control code (4 bits), the Chip Select (3 bits), and the
condition. This initiates the internal write cycle and,
WRITE OPERATIONS
Byte Write
4.2
The write control byte, word address and the first data
byte are transmitted to the 24XX32A in the same way
as in a byte write. However, instead of generating a
Stop condition, the master transmits up to 31 additional
bytes which are temporarily stored in the on-chip page
buffer and will be written into memory once the master
has transmitted a Stop condition. Upon receipt of each
word, the five lower Address Pointer bits are internally
incremented by ‘1’. If the master should transmit more
than 32 bytes prior to generating the Stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the Stop condition is received, an
internal write cycle will begin (Figure 4-2). If an attempt
is made to write to the array with the WP pin held high,
the device will acknowledge the command, but no write
cycle will occur, no data will be written, and the device
will immediately accept a new command.
4.3
The WP pin allows the user to write-protect the entire
array (000-FFF) when the pin is tied to V
V
sampled at the Stop bit for every Write command
(Figure 3-1). Toggling the WP pin after the Stop bit will
have no effect on the execution of the write cycle.
SS
Note:
24AA32A/24LC32A
the write protection is disabled. The WP pin is
Page Write
Write Protection
Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size (or
‘page size’) and end at addresses that are
integer multiples of [page size – 1]. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
DS21713H-page 7
CC
. If tied to