at25f512y4-10yu-2.7 ATMEL Corporation, at25f512y4-10yu-2.7 Datasheet

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at25f512y4-10yu-2.7

Manufacturer Part Number
at25f512y4-10yu-2.7
Description
At25f1024
Manufacturer
ATMEL Corporation
Datasheet

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Part Number
Manufacturer
Quantity
Price
Part Number:
AT25F512Y4-10YU-2.7
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Features
Description
The AT25F512/1024 provides 524,288/1,048,576 bits of serial reprogrammable Flash
memory organized as 65,536/131,072 words of 8 bits each. The device is optimized
for use in many industrial and commercial applications where low-power and low-volt-
age operation are essential. The AT25F512/1024 is available in a space-saving 8-lead
JEDEC SOIC and 8-lead SAP packages.
The AT25F512/1024 is enabled through the Chip Select pin (CS) and accessed via a
3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK). All write cycles are completely self-timed.
BLOCK WRITE protection for top 1/4, top 1/2 or the entire memory array (1M) or
entire memory array (512K) is enabled by programming the status register. Separate
write enable and write disable instructions are provided for additional data protection.
Hardware data protection is provided via the WP pin to protect against inadvertent
write attempts to the status register. The HOLD pin may be used to suspend any serial
communication without resetting the serial sequence.
Pin Configurations
Pin Name
CS
SCK
SI
SO
GND
VCC
WP
HOLD
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
20 MHz Clock Rate
Byte Mode and 256-byte Page Mode for Program Operations
Sector Architecture:
Product Identification Mode
Low-voltage Operation
Sector Write Protection
Write Protect (WP) Pin and Write Disable Instructions for
both Hardware and Software Data Protection
Self-timed Program Cycle (60 µs/Byte Typical)
Self-timed Sector Erase Cycle (1 second/Sector Typical)
Single Cycle Reprogramming (Erase and Program) for Status Register
High Reliability
Lead-free Devices Available
8-lead JEDEC SOIC and 8-lead SAP Packages
– Two Sectors with 32K Bytes Each (512K)
– Four Sectors with 32K Bytes Each (1M)
– 128 Pages per Sector
– 2.7 (V
– Endurance: 10,000 Write Cycles Typical
CC
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Power Supply
Write Protect
Suspends Serial Input
Function
= 2.7V to 3.6V)
GND
WP
SO
CS
HOLD
VCC
SCK
SI
Bottom View
8-lead SOIC
8-lead SAP
1
2
3
4
8
7
6
5
8
7
6
5
1
2
3
4
CS
SO
WP
GND
VCC
HOLD
SCK
SI
SPI Serial
Memory
512K (65,536 x 8)
1M (131,072 x 8)
AT25F512
AT25F1024
Rev. 1440P–SEEPR–6/04
1

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at25f512y4-10yu-2.7 Summary of contents

Page 1

... Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All write cycles are completely self-timed. BLOCK WRITE protection for top 1/4, top 1/2 or the entire memory array (1M) or entire memory array (512K) is enabled by programming the status register. Separate write enable and write disable instructions are provided for additional data protection. ...

Page 2

Absolute Maximum Ratings* Operating Temperature........................................−40°C to +85°C Storage Temperature .........................................−65°C to +150°C Voltage on Any Pin with Respect to Ground ........................................ −1.0V to +3.6V Maximum Operating Voltage ............................................ 3.6V DC Output Current........................................................ 5.0 mA Block Diagram AT25F512/1024 2 *NOTICE: Stresses ...

Page 3

Pin Capacitance Applicable over recommended operating range from T Symbol Test Conditions C Output Capacitance (SO) OUT C Input Capacitance (CS, SCK, SI, WP, HOLD) IN Note: 1. This parameter is characterized and is not 100% tested. DC Characteristics ...

Page 4

AC Characteristics Applicable over recommended operating range from TTL Gate and 30 pF (unless otherwise noted). L Symbol Parameter f SCK Clock Frequency SCK t Input Rise Time RI t Input Fall Time FI t SCK ...

Page 5

Serial Interface Description 1440P–SEEPR–6/04 MASTER: The device that generates the serial clock. SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25F512/1024 always operates as a slave. TRANSMITTER/RECEIVER: The AT25F512/1024 has separate pins designated for data transmission ...

Page 6

SPI Serial Interface AT25F512/1024 6 MASTER: MICROCONTROLLER DATA OUT (MOSI) DATA IN (MISO) SERIAL CLOCK (SPI CK) SS0 SS1 SS2 SS3 SLAVE: AT25F512/1024 SI SO SCK SCK SCK SCK CS 1440P–SEEPR–6/04 ...

Page 7

... Set Write Enable Latch Reset Write Enable Latch Read Status Register Write Status Register Read Data from Memory Array Program Data Into Memory Array Erase One Sector in Memory Array Erase All Sectors in Memory Array Read Manufacturer and Product ID Bit 4 Bit 3 Bit 2 Bit 1 X ...

Page 8

... WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protection for the AT25F1024. The AT25F1024 is divided into four sectors where the top quarter (1/4), top half (1/2), or all of the memory sectors can be protected (locked out) from write. The AT25F512 is divided into 2 sectors where all of the memory sectors can be protected (locked out) from write ...

Page 9

... For the AT25F1024, when the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous READ instruction. For the AT25F512, the read command must be termi- nated when the highest address (00FFFF) is reached ...

Page 10

AT25F512/1024 10 The READY/BUSY status of the device can be determined by initiating a RDSR instruc- tion. If Bit the program cycle is still in progress. If Bit the program cycle has ended. Only ...

Page 11

Timing Diagrams (for SPI Mode 0 (0, 0)) Synchronous Data Timing CSS V IH SCK HI WREN Timing WRDI Timing ...

Page 12

RDSR Timing CS 0 SCK INSTRUCTION SI HIGH IMPEDANCE SO WRSR Timing READ Timing SCK SI INSTRUCTION HIGH IMPEDANCE SO AT25F512/1024 MSB 3 4 ...

Page 13

PROGRAM Timing SCK SI INSTRUCTION HIGH IMPEDANCE SO HOLD Timing CS SCK HOLD SO SECTOR ERASE Timing X = Don’t Care bit 1440P–SEEPR–6/ ...

Page 14

CHIP ERASE Timing RDID Timing AT25F512/1024 Don’t Care bit MANUFACTURER CODE (ATMEL DEVICE CODE 1440P–SEEPR–6/04 ...

Page 15

... Ordering Information Ordering Code AT25F512N-10SI-2.7 AT25F1024N-10SI-2.7 AT25F512N-10SU-2.7 AT25F512Y4-10YU-2.7 AT25F1024N-10SU-2.7 AT25F1024Y4-10YU-2.7 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8Y4 8-lead, 6. 4.90 mm Body, Dual Footprint, Non-leaded, Small Array Package (SAP) -2.7 Low-voltage (2.7V to 3.6V) 1440P–SEEPR–6/04 Package 8S1 8S1 8S1 ...

Page 16

Package Drawing 8S1 – JEDEC SOIC Top View e Side View Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO ...

Page 17

SAP PIN 1 INDEX AREA D E 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80817 R 1440P–SEEPR–6/04 A PIN COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN A – A1 0.00 ...

Page 18

... Fax: (81) 3-3523-7581 Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...

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