is43dr16320b-3dbi Integrated Silicon Solution, Inc., is43dr16320b-3dbi Datasheet - Page 17

• Manufacturer Part Number: is43dr16320b-3dbi
• Description: 512mb X8, X16 Ddr2 Sdram
• Manufacturer: Integrated Silicon Solution, Inc.

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IS43DR86400B, IS43/46DR16320B
Output Buffer Characteristics
Output AC Test Conditions
Note: The VDDQ of the device under test is referenced.
Output DC Current Drive
Notes:
1.
2.
3.
4.
OCD Default Characteristics
Notes:
1.
2.
3.
4.
Output Capacitance
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00B, 12/11/2009
Symbol
VOTR
Symbol
IOH(DC)
IOL(DC)
Paramater
Input Capacitance (CK and CK#)
Input Capacitance Delta (CK and CK#)
Input Capacitance (all other input‐only pins)
Input Capacitance Delta (all other input‐only
pins)
I/O Capacitance (DQ, DM, DQS, DQS#)
I/O Capacitance Delta (DQ, DM, DQS, DQS#)
Output impedance step size for OCD calibration
A 0 Ω value (no calibration) can only be achieved if the OCD impedance is 18 Ω ±0.75 Ω under nominal conditions.
DRAM output slew rate specification applies to 667 MT/s speed bins.
Timing skew due to DRAM output slew rate mismatch between DQS/DQS# and associated DQ’s is included in tDQSQ and tQHS specification.
VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT ‐ VDDQ)/IOH must be less than 21 Ω for values of VOUT between VDDQ and VDDQ ‐ 280 mV.
VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 Ω for values of VOUT between 0 V and 280 mV.
The DC value of VREF applied to the receiving device is set to VTT
The values of IOH(DC) and IOL(DC) are based on the conditions given in Notes 1 and 2. They are used to test device drive current capability to ensure VIH(Min)
plus a noise margin and VIL(Max) minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver
operating point (see Section 3.3 of JESD8‐15A) along a 21 Ω load line to define a convenient driver current for measurement.
Absolute Specifications (TOPER; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V). DRAM I/O specifications for timing, voltage, and slew rate are no longer applicable if
OCD is changed from default settings.
Impedance measurement condition for output source DC current: VDDQ = 1.7 V; VOUT = 1420 mV; (VOUT‐VDDQ)/IOH must be less than 23.4 Ω for values of
VOUT between VDDQ and VDDQ ‐ 280 mV. Impedance measurement condition for output sink DC current: VDDQ = 1.7 V; VOUT = 280 mV; VOUT/IOL must be
less than 23.4 Ω for values of VOUT between 0 V and 280 mV.
Mismatch is absolute value between pull‐up and pull‐down, both are measured at same temperature and voltage.
Slew rate measured from VIL(AC) to VIH(AC).
The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is guaranteed by
design and characterization.
This represents the step size when the OCD is near 18 Ω at nominal conditions across all process corners/variations and represents only the DRAM uncertainty.
Pull‐up and pull‐down mismatch
Output Impedance
Output slew rate
Description
Output Minimum Source DC Current
Output Minimum Sink DC Current
Output Timing Measurement Reference Level
Parameter
Parameter
SOUT
Symbol
Parameter
CDCK
CDIO
CCK
CDI
CIO
CI
‐5B (DDR2‐400B)/
‐37C (DDR2‐533C)
Min.
1.00
1.00
2.50
Min
See full strength default driver characteristics
1.5
0
0
Max
2.00
0.25
2.00
0.25
4.00
0.50
Normal 18 ohms
Nom.
‐3D (DDR2‐667D)
1.00
1.00
2.50
Min
SSTL_18
‐13.4
13.4
Max.
1.5
4
5
Max
2.00
0.25
2.00
0.25
3.50
0.50
0.5 x VDDQ
SSTL_18
‐25E (DDR2‐800E)/
‐25D (DDR2‐800D)
1.00
1.00
2.50
Min
ohms
ohms
ohms
Units
V/ns
Units
mA
mA
Max
2.00
0.25
1.75
0.25
3.50
0.50
1, 4, 5, 7, 8
Units
Notes
1, 2, 3
1, 2
V
Notes
1, 3, 4
2, 3, 4
6
Units
17
pF
pF
pF
pF
pF
pF