is43dr16320b-3dbi Integrated Silicon Solution, Inc., is43dr16320b-3dbi Datasheet - Page 23

• Manufacturer Part Number: is43dr16320b-3dbi
• Description: 512mb X8, X16 Ddr2 Sdram
• Manufacturer: Integrated Silicon Solution, Inc.

10. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus
15. Timings are guaranteed with command / address input slew rate of 1.0 V/ns.
IS43DR86400B, IS43/46DR16320B
AC Characteristics
(AC Operating Conditions Unless Otherwise Noted)
Average Periodic Refresh
Interval (Tc = ‐40°C to +85° C)
Average Periodic Refresh
Interval (Tc = +85°C to +95° C)
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
11. A maximum of eight Auto‐Refresh commands can be posted to any given DDR2 SDRAM device. (Note: tRFC depends on DRAM density)
12. For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter
13. Parameter tWTR is at least two clocks independent of operation frequency.
14. User can choose two different active power‐down modes for additional power saving via MRS address bit A12. In “standard active power‐down mode” (MRS,
16. Timings are guaranteed with data / mask input slew rate of 1.0 V/ns.
17. Timings are guaranteed with CK/CK# differential slew rate 2.0 V/ns, and DQS/DQS# (and RDQS/RDQS#) differential slew rate 2.0 V/ns in differential strobe
18. If refresh timing or tDS/tDH is violated, data corruption may occur and the data must be re‐written with valid data before a valid READ can be executed.
19. In all circumstances, tXSNR can be satisfied using tXSNR = tRFC + 10 ns.
20. The tRCD timing parameter is valid for both activate command to read or write command with and without Auto‐Precharge. Therefore a separate parameter
21.
22. Definitions:
23. Supported only for industrial and automotive grades. TOPER must not be violated.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00B, 12/11/2009
When programmed in differential strobe mode, DQS is always the logic complement of DQS except when both are in high‐Z.
Input slew rate is 1 V/ns and AC timings are guaranteed for linear signal transitions.
The CK/CK# input reference level (for timing reference to CK/CK#) is the point at which CK and CK# cross the DQS/DQS# input reference level is the cross point
when in differential strobe mode; the input reference level for signals other than CK/CK#, or DQS/DQS# is VREF.
Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as LOW.
The output timing reference voltage level is VTT.
The values tCL(Min) and tCH(Min) refer to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be
greater than the minimum specification limits for tCL and tCH.
For input frequency change during DRAM operation.
Transitions for tHZ and tLZ occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but
specify when the device is no longer driving (HZ), or begins driving (LZ).
These parameters guarantee device timing, but they are not necessarily tested on each device.
The specific requirement is that DQS and DQS# be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined
as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning
from Hi‐Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
turnaround) degrades accordingly.
stored in the MRS.
A12 = “0”) a fast power‐down exit timing tXARD can be used. In “low active power‐down mode” (MRS, A12 =”1”) a slow power‐down exit timing tXARDS has to
be satisfied.
mode.
tRAP for activate command to read or write command with Auto‐Precharge is not necessary anymore.
tRAS(max) is calculated from the maximum amount of time a DDR2 device can operate without a Refresh command which is equal to 9 x tREFI.
a.
b.
c.
d.
e.
f.
g.
Parameter
tCK(avg): tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window.
tCH(avg): tCH(avg) is defined as the average HIGH pulse width, as calculated across any consecutive 200 HIGH pulses.
tCL(avg): tCL(avg) is defined as the average LOW pulse width, as calculated across any consecutive 200 LOW pulses.
tJITDTY: tJITDTY is defined as the cumulative set of tCH jitter and tCL jitter. tCH jitter is the largest deviation of any single tCH from tCH(avg). tCL jitter
is the largest deviation of any single tCL from tCL(avg)
tJITPER: tJITPER is defined as the largest deviation of any single tCK from tCK(avg).
tJITCC: tJITCC is defined as the difference in clock period between two consecutive clock cycles: tJITCC is not guaranteed through final production
testing
tERR: tERR is defined as the cumulative error across multiple consecutive cycles from tCK (avg).
Symbol
tREFI
tREFI
DDR2‐400B
Min Max Min Max Min Max Min Max Min Max
‐5B
7.8
3.9
DDR2‐533C
‐37C
7.8
3.9
DDR2‐667D
‐3D
7.8
3.9
DDR2‐800E
‐25E
7.8
3.9
DDR2‐800D
‐25D
7.8
3.9
Units Notes
μs
μs 18, 23
18
23