is43dr16320-3dbli Integrated Silicon Solution, Inc., is43dr16320-3dbli Datasheet - Page 4

• Manufacturer Part Number: is43dr16320-3dbli
• Description: 512mb X8, X16 Ddr2 Sdram
• Manufacturer: Integrated Silicon Solution, Inc.

2. Start clock and maintain stable condition.
3. For the minimum of 200 µs after stable power (VDD, VDDL, VDDQ, VREF, and VTT values are in the range of the minimum and
4. Wait minimum of 400 ns then issue a precharge all command. During the 400 ns period, a NOP or Deselect command must be
5. Issue an EMRS command to EMR(2).
6. Issue an EMRS command to EMR(3).
7. Issue EMRS to enable DLL.
8. Issue a Mode Register Set command for DLL reset.
9. Issue a precharge all command.
10. Issue 2 or more auto‐refresh commands.
11. Issue a MRS command with LOW to A8 to initialize device operation. (i.e. to program operating parameters without resetting
12. Wait at least 200 clock cycles after step 8 and then execute OCD Calibration (Off Chip Driver impedance adjustment). If OCD
13. The DDR2 SDRAM is now ready for normal operation.
Note*: To guarantee ODT off, VREF must be valid and a LOW level must be applied to the ODT pin.
IS43DR86400, IS43/46DR16320
Functional Description
Power‐up and Initialization
DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may
result in undefined operation.
Power‐up and Initialization Sequence
The following sequence is required for Power‐up and Initialization.
1. Either one of the following sequence is required for Power‐up:
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00A, 11/17/2009
maximum values specified in the table Recommended DC Operating Conditions (SSTL‐1.8)) and stable clock (CK, CK#), then apply
NOP or Deselect and assert a logic HIGH to CKE.
issued to the DRAM.
the DLL.)
calibration is not used, EMRS Default command (A9=A8=A7=HIGH) followed by EMRS OCD Calibration Mode Exit command
(A9=A8=A7=LOW) must be issued with other operating parameters of EMR(1).
A. While applying power, attempt to maintain CKE below 0.2 x VDDQ and ODT* at a LOW state (all other inputs may be
B. While applying power, attempt to maintain CKE below 0.2 x VDDQ and ODT* at a LOW state (all other inputs may be
Operating Conditions (SSTL_1.8), prevail.
−
ramping of the supply voltages is complete, the supply voltage specifications provided in the table Recommended DC
Operating Conditions (SSTL‐1.8), prevail.
−
−
−
−
undefined.) The VDD voltage ramp time must be no greater than 200 ms from when VDD ramps from 300 mV to
VDD(Min); and during the VDD voltage ramp, |VDD‐VDDQ| ≥ 0.3 V. Once the ramping of the supply voltages is
complete (when VDDQ crosses VDDQ(Min)), the supply voltage specifications provided in the table Recommended DC
−
−
−
undefined, voltage levels at I/Os and outputs must be less than VDDQ during voltage ramp time to avoid DRAM latch‐
up. During the ramping of the supply voltages, VDD ≥ VDDL ≥ VDDQ must be maintained and is applicable to both AC
and DC levels until the ramping of the supply voltages is complete, which is when VDDQ crosses VDDQ min. Once the
Apply VDD/VDDL before or at the same time as VDDQ.
VDD/VDDL voltage ramp time must be no greater 200 ms from when VDD ramps from 300 mV to VDD(Min) .
Apply VDDQ before or at the same time as VTT.
must be no greater than 500 ms.
VDD, VDDL and VDDQ are driven from a single power converter output, AND
VTT is limited to 0.95V max, AND
VREF tracks VDDQ/2, VREF must be within ± 300mV with respect to VDDQ/2 during supply ramp time.
VDDQ ≥ VREF must be met at all times
The VDDQ voltage ramp time from when VDD(Min) is achieved on VDD to the VDDQ(Min) is achieved on VDDQ
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