w25x32a Winbond Electronics Corp America, w25x32a Datasheet
w25x32a
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w25x32a Summary of contents
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... SERIAL FLASH MEMORY WITH 4KB SECTORS AND DUAL OUTPUT SPI Publication Release Date: August 24, 2008 - 1 - W25X32A Preliminary - Revision A ...
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... CONTROL AND STATUS REGISTERS ........................................................................................ 12 11.1 STATUS REGISTER .......................................................................................................... 12 11.1.1 BUSY..................................................................................................................................12 11.1.2 Write Enable Latch (WEL) ..................................................................................................12 11.1.3 Block Protect Bits (BP2, BP1, BP0)....................................................................................12 11.1.4 Top/Bottom Block Protect (TB)...........................................................................................12 11.1.5 Reserved Bits .....................................................................................................................12 11.1.6 Status Register Protect (SRP)............................................................................................13 11.1.7 Status Register Memory Protection ....................................................................................14 11.2 INSTRUCTIONS................................................................................................................. 15 11.2.1 Manufacturer and Device Identification ..............................................................................15 11.2.2 Instruction Set ....................................................................................................................16 11.2.3 Write Enable (06h)..............................................................................................................17 Table of Contents - 2 - W25X32A ...
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... Hold Timing ....................................................................................................................... 38 13 PACKAGE SPECIFICATION.......................................................................................................... 39 13.1 8-Pin SOIC 208-mil (Package Code SS) ........................................................................... 39 13.2 8-Pin PDIP 300-mil (Package Code DA)............................................................................ 40 13.3 8-Contact 6x5mm WSON (Package Code ZP) .................................................................. 41 13.4 16-Pin SOIC 300-mil (Winbond Package Code SF) .......................................................... 43 14 ORDERING INFORMATION .......................................................................................................... 44 15 REVISION HISTORY...................................................................................................................... 46 Publication Release Date: August 24, 2008 - 3 - W25X32A Preliminary - Revision A ...
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... Page Program instruction. Pages can be erased in groups of 16 (sector erase), groups of 256 (block erase) or the entire chip (chip erase). The W25X32A has 1,024 erasable sectors and 64 erasable blocks. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage ...
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... Figure 1a. W25X32A Pin Assignments, 8-pin SOIC 208-mil (Package Code SS) 4 PAD CONFIGURATION WSON 6X5-MM Figure 1b. W25X32A Pad Assignments, 8-pad WSON 6x5-mm (Package Code ZP) 5 PIN CONFIGURATION PDIP 300-MIL Figure 1c. W25X32A Pin Assignments, 8-pin PDIP 300-mil (Package Code DA) Publication Release Date: August 24, 2008 - 5 - W25X32A Preliminary - Revision A ...
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... DO 3 /WP 4 GND 5 DIO 6 CLK 7 /HOLD 8 VCC 7 PIN CONFIGURATION SOIC 300-MIL Figure 1d. W25X32A Pin Assignments, 16-pin SOIC 300-mil (Package Code SF) I/O FUNCTION I Chip Select Input O Data Output I Write Protect Input Ground I/O Data Input / Output I Serial Clock Input I Hold Input Power Supply ...
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... GND 11 N/C 12 N/C 13 N/C 14 N/C 15 DIO 16 CLK I/O FUNCTION I Hold Input Power Supply No Connect No Connect No Connect No Connect I Chip Select Input O Data Output I Write Protect Input Ground No Connect No Connect No Connect No Connect I/O Data Input / Output I Serial Clock Input Publication Release Date: August 24, 2008 - 7 - W25X32A Preliminary - Revision A ...
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... Package Types W25X32A is offered in an 8-pin plastic 208-mil width SOIC (package code SS), 6x5-mm WSON (package code ZP), 16-pin plastic 300-mil width SOIC (package code SF) and 300-mil DIP (package code DA). See figures 1a-d. Package diagrams and dimensions are illustrated at the end of this datasheet. 8.2 Chip Select (/CS) The SPI Chip Select (/CS) pin enables and disables the device operation. When /CS is high the device is deselected and the Serial Data Output (DO) pin is at high impedance. When deselected, the device’ ...
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... CLK CLK SPI SPI /CS /CS Command & Command & Control Logic Control Logic DIO DIO DO DO Figure 2. W25X32A Serial Flash Memory Block Diagram 3FFF00h 3FFF00h • • 3F0000h 3F0000h • • • • • • 20FF00h 20FF00h • • ...
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... All other operations use the standard SPI interface with single output signal. 10.1.3 Hold Function The /HOLD signal allows the W25X32A operation to be paused while it is actively selected (when /CS is low). The /HOLD function may be useful in cases where the SPI data and clock signals are shared with other devices ...
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... Hardware write protection using Status Register and /WP pin. • Write Protection using Power-down instruction. Upon power- power-down the W25X32A will maintain a reset condition while VCC is below the threshold value (See Power-up Timing and Voltage Levels and Figure 20). While reset, all WI operations are disabled and no instructions are recognized ...
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... Status register bit location S6 is reserved for future use. Current devices will read 0 for this bit location recommended to mask out the reserved bit when testing the Status Register. Doing this will ensure compatibility with future devices characteristics). All, none or a portion of the memory array can W25X32A , ...
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... When the SRP pin is set the Write Status Register instruction is locked out while the /WP pin is low. When the /WP pin is high the Write Status Register instruction is allowed. Figure 3. Status Register Bit Locations Publication Release Date: August 24, 2008 - 13 - W25X32A Preliminary - Revision A ...
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... Note don’t care W25X32A (32M-BIT) MEMORY PROTECTION BLOCK(S) ADDRESSES NONE NONE 63 3F0000h – 3FFFFFh 62 and 63 3E0000h – 3FFFFFh 60 thru 63 3C0000h – 3FFFFFh 56 thru 63 380000h – 3FFFFFh 48 thru 63 300000h – 3FFFFFh 32 thru 63 200000h – 3FFFFFh 0 000000h – ...
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... INSTRUCTIONS The instruction set of the W25X32A consists of fifteen basic instructions that are fully controlled through the SPI bus (see Instruction Set table). Instructions are initiated with the falling edge of Chip Select (/CS). The first byte of data clocked into the DIO input provides the instruction code. Data on the DIO input is sampled on the rising edge of clock with most significant bit (MSB) first ...
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... A15–A8 A7–A0 (D7–D0) A15–A8 A7–A0 A15–A8 A7–A0 dummy dummy (ID7-ID0) dummy 00h (M7-M0) (ID15-ID8) (ID7-ID0) Memory Capacity Type - 16 - W25X32A BYTE 6 N-BYTES (2) (Next byte) continuous (Next Byte) (D7–D0) continuous I/O = (one byte (D6,D4,D2,D0) per 4 clocks continuous) (D7,D5,D3,D1 256 (Next byte) bytes (4) ...
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... DIO pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase and Chip Erase instructions. Figure 4. Write Enable Instruction Sequence Diagram Figure 5. Write Disable Instruction Sequence Diagram - 17 - W25X32A Publication Release Date: August 24, 2008 Preliminary - Revision A ...
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... Status Register cycle is in progress. This allows the BUSY status bit to be checked to determine when the cycle is complete and if the device can accept another instruction. The Status Register can be read continuously, as shown in Figure 6. The instruction is completed by driving /CS high. Figure 6. Read Status Register Instruction Sequence Diagram - 18 - W25X32A ...
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... When the SRP pin is set the Write Status Register instruction is locked out while the /WP pin is low. When the /WP pin is high the Write Status Register instruction is allowed. Figure 7. Write Status Register Instruction Sequence Diagram (See AC Characteristics). While the Write W Publication Release Date: August 24, 2008 - 19 - W25X32A Preliminary - Revision A ...
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... The Read Data instruction sequence is shown in figure Read Data instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any effects on the current cycle. The Read Data instruction allows clock rates from D. maximum of f (see AC Electrical Characteristics). Figure 8. Read Data Instruction Sequence Diagram - 20 - W25X32A R ...
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... The dummy clocks allow the devices internal circuits additional time for setting up the initial address. During the dummy clocks the data value on the DIO pin is a “don’t care”. Figure 9. Fast Read Instruction Sequence Diagram - 21 - W25X32A Publication Release Date: August 24, 2008 Preliminary - Revision A ...
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... DO and DIO, instead of just DO. This allows data to be transferred from the W25X32A at twice the rate of standard SPI devices. The Fast Read Dual Output instruction is ideal for quickly downloading code from Flash to RAM upon power-up or for applications that cache code- segments to RAM for execution ...
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... The Page Program instruction will not be executed if the addressed page is protected by the Block Protect (BP2, BP1, and BP0) bits (see Status Register Memory Protection table). Figure 11. Page Program Instruction Sequence Diagram Publication Release Date: August 24, 2008 - 23 - W25X32A Preliminary - Revision A ...
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... Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector Erase instruction will not be executed if the addressed page is protected by the Block Protect (TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table). (See AC Characteristics). While the Sector Erase SE Figure 12. Sector Erase Instruction Sequence Diagram - 24 - W25X32A ...
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... Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be executed if the addressed page is protected by the Block Protect (TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection table). (See AC Characteristics). While the Block Erase cycle BE Figure 13. Block Erase Instruction Sequence Diagram - 25 - W25X32A Publication Release Date: August 24, 2008 Preliminary - Revision A ...
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... Status Register is cleared to 0. The Chip Erase instruction will not be executed if any page is protected by the Block Protect (BP2, BP1, and BP0) bits (see Status Register Memory Protection table). (See AC Characteristics). While the Chip Erase cycle is in progress, CE Figure 14. Chip Erase Instruction Sequence Diagram - 26 - W25X32A ...
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... Ignoring all but one instruction makes the Power Down state a useful condition for securing maximum write protection. The device always powers-up in the normal operation with the standby current of ICC1. Figure 15. Deep Power-down Instruction Sequence Diagram Publication Release Date: August 24, 2008 - 27 - W25X32A Preliminary - Revision A ...
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... The Device ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure 17. The Device ID value for the W25X32A is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The instruction is completed by driving /CS high. ...
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... Figure 17. Release Power-down / Device ID Instruction Sequence Diagram - 29 - W25X32A Publication Release Date: August 24, 2008 Preliminary - Revision A ...
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... Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure 18. The Device ID value for the W25X32A is listed in Manufacturer and Device Identification table. If the 24-bit address is initially set to 000001h the Device ID will be read first and then followed by the Manufacturer ID ...
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... JEDEC ID (9Fh) For compatibility reasons, the W25X32A provides several instructions to electronically determine the identity of the device. The Read JEDEC ID instruction is compatible with the JEDEC standard for SPI compatible serial memories that was adopted in 2003. The instruction is initiated by driving the /CS pin low and shifting the instruction code “9Fh”. The JEDEC ...
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... Electrostatic Discharge Voltage Notes: 1. Specification for W25X32A is preliminary. See preliminary designation at the end of this document. 2. This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is not guaranteed. Exposure to absolute maximum ratings may affect device reliability. ...
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... Time Delay Before Write Instruction Write Inhibit Threshold Voltage Note: 1. These parameters are characterized only. SYMBOL MIN t (1) 10 VSL t (1) 1 PUW V 1 (1) WI Figure 20. Power-up Timing and Voltage Levels - 33 - W25X32A SPEC UNIT MAX µ Publication Release Date: August 24, 2008 Preliminary - Revision A ...
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... VIN = GND or VCC C = 0.1 VCC / 0.9 VCC DO = Open C = 0.1 VCC / 0.9 VCC DO = Open C = 0.1 VCC / 0.9 VCC DO = Open C = 0.1 VCC / 0.9 VCC DO = Open /CS = VCC /CS = VCC /CS = VCC /CS = VCC –0.5 VCC x0 1 –100 µA VCC –0 W25X32A SPEC UNIT TYP MAX ±2 µA ±2 µ µA <1 10 µA 5/6 7/8 mA 7/8 ...
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... Note: 1. Output Hi-Z is defined as the point where data out is no longer driven. SYMBOL MIN 0.2 VCC to 0.8 VCC IN 0.3 VCC to 0.7 VCC IN O 0.5 VCC to 0.5 VCC UT Figure 21. AC Measurement I/O Waveform Publication Release Date: August 24, 2008 - 35 - W25X32A SPEC UNIT MAX Preliminary - Revision A ...
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... SLCH CSS t CHSL t t DVCH DSU t t CHDX DH t CHSH t SHCH Array Read / t t SHSL CSH ( SHQZ DIS t t CLQV CLQX W25X32A SPEC UNIT MIN TYP MAX D.C. 75 MHz D.C. 33 MHz 0.1 V/ns 0.1 V/ 50/100 ns 7 ...
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... DP ( RES ( RES t W (4) t BP1 (4) t BP2 (typical) and BPN BP1 + BP2 * W25X32A SPEC ALT MIN TYP MAX 100 1.6 3 120 200 0. ...
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... Serial Output Timing 12.9 Input Timing 12.10 Hold Timing - 38 - W25X32A ...
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... Formed leads shall be planar with respect to one another within .0004 inches at the seating plane. MILLIMETERS INCHES MIN MAX MIN 1.75 2.16 0.069 0.05 0.25 0.002 1.70 1.91 0.067 0.35 0.48 0.014 0.19 0.25 0.007 5.18 5.38 0.204 7.70 8.10 0.303 5.18 5.38 0.204 1.27 BSC 0.050 BSC 0.50 0.80 0.020 --- 0.10 --- Publication Release Date: August 24, 2008 - 39 - W25X32A MAX 0.085 0.010 0.075 0.019 0.010 0.212 0.319 0.212 0.031 8 o 0.004 Preliminary - Revision A ...
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... W25X32A INCHES TYP. MAX --- 0.210 --- --- 0.130 0.135 0.018 0.022 0.060 0.064 0.010 0.014 0.365 0.400 0.300 0.310 0.250 0.255 0.100 0.110 0.130 0.150 7 15 ...
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... BSC 0.20 0.0080 0.50 0.60 0.75 0.0197 - 41 - W25X32A INCHES MIN TYP. MAX 0.0295 0.0315 0.0008 0.0019 0.0126 0.0080 0.0098 0.0157 0.0190 0.2360 0.2400 0.1338 0.1377 0.1970 0.2010 0.1692 0.1732 0.0500 BSC 0.0236 0.0295 Publication Release Date: August 24, 2008 Preliminary - Revision A ...
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... Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. The metal pad area on the bottom center of the package is connected to the device ground (GND pin). Avoid placement of exposed PCB vias under the pad. INCHES T YP. MAX MIN 3.40 0.13 8 4.30 0.16 2 6.00 0.23 0 0.50 0.01 6 0.75 0. W25X32A TYP. MAX ...
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... Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. MILLIMETERS INCHES MIN MAX MIN 2.36 2.64 0.093 0.10 0.30 0.004 0.33 0.51 0.013 0.18 0.28 0.007 10.08 10.49 0.397 10.01 10.64 0.394 7.39 7.59 0.291 1.27 BSC 0.050 BSC 0.39 1.27 0.015 --- 0.076 --- Publication Release Date: August 24, 2008 - 43 - W25X32A MAX 0.104 0.012 0.020 0.011 0.413 0.419 0.299 0.050 8 o 0.003 Preliminary - Revision A ...
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... WSON package type ZP is not used for the top marking. 1b. Standard bulk shipments are in Tube (shape E). Please specify alternate packing method, such as Tape and Reel (shape T), when placing orders. 1c. The “W” prefix is not included on the part marking. ( W25X32A ...
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... WSON-8 6x5mm DA 32M-bit PDIP-8 300mil Notes: 1. For WSON packages, the package type ZP are not used in the top side marking. PRODUCT NUMBER TOP SIDE MARKING W25X32AVSSIG W25X32AVSFIG W25X32AVZPIG W25X32AVDAIG W25X32AVDAIZ Publication Release Date: August 24, 2008 - 45 - W25X32A 25X32AVSIG 25X32AVFIG 25X32AVIG 25X32AVAIG 25X32AVAIZ Preliminary - Revision A ...
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... Information in this document is provided solely in connection with Winbond products. Winbond reserves the right to make changes, corrections, modifications or improvements to this document and the products and services decribed herein at any time, without notice. PAGE DESCRIPTION All New Create Preliminary - 46 - W25X32A ranteed. Winbond ...