w9425g6eb Winbond Electronics Corp America, w9425g6eb Datasheet
w9425g6eb
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w9425g6eb Summary of contents
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... Data Write Enable /Disable Command .................................................................................12 7.3 Read Operation ................................................................................................................................12 7.4 Write Operation ................................................................................................................................13 7.5 Precharge.........................................................................................................................................13 7.6 Burst Termination .............................................................................................................................13 7.7 Refresh Operation ............................................................................................................................13 7.8 Power Down Mode ...........................................................................................................................14 7.9 Input Clock Frequency Change during Precharge Power Down Mode ............................................14 7.10 Mode Register Operation .................................................................................................................14 7.10.1 Burst Length field (A2 to A0) ................................................................................................14 7.10.2 Addressing Mode Select (A3)...............................................................................................15 W9425G6EB Publication Release Date:Feb. 12, 2009 - 1 - Revision A02 ...
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... Command Input Timing ....................................................................................................................33 11.2 Timing of the CLK Signals ................................................................................................................33 11.3 Read Timing (Burst Length = 4) .......................................................................................................34 11.4 Write Timing (Burst Length = 4) .......................................................................................................35 11.5 DM, DATA MASK (W9425G6EB).....................................................................................................36 11.6 Mode Register Set (MRS) Timing.....................................................................................................37 11.7 Extend Mode Register Set (EMRS) Timing ......................................................................................38 11.8 Auto-precharge Timing (Read Cycle ..................................................................................39 11.9 Auto-precharge Timing (Read cycle 2), continued..................................................................40 11 ...
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... Precharged/Active Power Down Mode Entry and Exit Timing ..........................................................48 11.25 Input Clock Frequency Change during Precharge Power Down Mode Timing.................................48 11.26 Self Refresh Entry and Exit Timing...................................................................................................49 12. PACKAGE SPECIFICATION .......................................................................................................................50 12.1 Package Outline TFBGA 60 Ball (8x13 mm 13. REVISION HISTORY ...................................................................................................................................51 W9425G6EB 2 )...................................................................................50 Publication Release Date:Feb. 12, 2009 - 3 - Revision A02 ...
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... SDRAM), organized as 4,194,304 words × 4 banks × 16 bits. W9425G6EB delivers a data bandwidth 400M words per second (-5). To fully comply with the personal computer industrial standard, W9425G6EB is sorted into two speed grades: -5 and -6I. The -5 is compliant to the DDR400/CL3 specification. The -6I is compliant to the DDR333/CL3 specification (the -6I grade which is guaranteed to support -40° ...
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... DD0 I Operating Current: One Bank Active-Read-Precharge DD1 I Burst Operation Read Current DD4R I Burst Operation Write Current DD4W I Auto Refresh Current DD5 I Self Refresh Current DD6 W9425G6EB MIN./MAX. Min. 7 Max. Min 2.5 Max. Min Max. Min. Min. Max. 110 mA Max. ...
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... D E LDQS VDDQ DQ7 F G LDM VDD CAS K L RAS CS M BA1 BA0 A0 A10/ VDD A3 Publication Release Date:Feb. 12, 2009 - 6 - W9425G6EB : Ball Existing : Depopulated Ball 1.0 mm 0.8 mm 8.0 mm BGA Package Ball Pattern Top View Revision A02 13.0 mm ...
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... Ground for logic circuit inside DDR SDRAM. Separated power from V I/O Buffer improve noise. Ground for I/O Separated ground from V Buffer improve noise. No Connection No connection - 7 - W9425G6EB DESCRIPTION ) define the command CS , used for output buffer used for output buffer Publication Release Date:Feb. 12, 2009 Revision A02 ...
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... CELL ARRAY BANK #0 SENSE AMPLIFIER PREFETCH REGISTER DATA CONTROL CIRCUIT COLUMN DECODER CELL ARRAY BANK #2 SENSE AMPLIFIER NOTE: The cell array configuration is 8192 * 512 * W9425G6EB COLUMN DECODER CELL ARRAY BANK #1 SENSE AMPLIFIER DQ0 DQ BUFFER DQ15 LDQS UDQS COLUMN DECODER CELL ARRAY ...
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... DDQ and V TT MRS PREA AREF 2 Clock min 200 Clock min. DLL reset with A8 = High Initialization sequence after power- W9425G6EB . REF AREF MRS t RFC 2 Clock min. t RFC Disable DLL reset with A8 = Low Publication Release Date:Feb. 12, 2009 Revision A02 ANY CMD ...
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... Read with Auto-precharge Command ( RAS = "H", CAS = ”L” ”H”, BA0, BA1 = Bank, A10 = ”H” Column Address) The Read with Auto-precharge command automatically performs the Precharge operation after the Read operation. W9425G6EB Publication Release Date:Feb. 12, 2009 - 10 - Revision A02 ...
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... The refresh addressing is generated by the internal refresh controller. This makes the address bits ”Don’t Care” during an AUTO REFRESH command. The DDR SDRAM requires AUTO REFRESH cycles at an average periodic interval (BL/ W9425G6EB Publication Release Date:Feb. 12, 2009 Revision A02 ...
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... Read cycle then the bank is switched to the idle state. This command cannot be interrupted by any other commands. Refer to the diagrams for Read operation. because time is required for the completion of any internal refresh in from the Bank Activate command, the data is read out sequentially W9425G6EB REFI Publication Release Date:Feb. 12, 2009 Revision A02 . ...
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... After exiting from the Self Refresh mode, the refresh operation must be performed within 7.8 µS. In Self Refresh mode, all input/output buffers are disabled, from the bank activate command. The input data is latched RCD from the bank activate command. RAS(max) . RFC Publication Release Date:Feb. 12, 2009 - 13 - W9425G6EB . Therefore, each RAS (max) Revision A02 ...
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... This field specifies the data length for column access using the pins and sets the Burst Length and 8 words BURST LENGTH 0 Reserved 1 2 words 0 4 words 1 8 words x Reserved Publication Release Date:Feb. 12, 2009 - 14 - W9425G6EB Revision A02 ...
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... words (address bit A0, A1) Not carried from words (address bits A2, A1 and A0) Not carried from Addressing Sequence of Interleave Mode ACCESS ADDRESS - 15 - W9425G6EB BURST LENGTH BURST LENGTH 2 words 4 words 8 words Publication Release Date:Feb. 12, 2009 Revision A02 ...
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... A4 CAS LATENCY A12-A0 Regular MRS Cycle Extended MRS Cycle Reserved DLL Enable Disable A1 BUFFER STRENGTH Publication Release Date:Feb. 12, 2009 - 16 - W9425G6EB Reserved Reserved 2 3 Reserved Reserved 2.5 Reserved 100% Strength 60% Strength Reserved 30% Strength Revision A02 ...
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... This bit is used to enter Test mode and must be set to "0" for normal operation. • Reserved bits (A9, A10, A11, A12) These bits are reserved for future operations. They must be set to "0" for normal operation. W9425G6EB Publication Release Date:Feb. 12, 2009 - 17 - Revision A02 ...
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... CKE signal is input level one clock cycle before the commands are issued. 3. These are state designated by the BA0, BA1 signals. 4. LDM, UDM (W9425G6EB). 5. Power Down Mode can not entry in the burst cycle. BA0, (4) CKEn-1 CKEn ...
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... BST BA, CA, A10 READ/READA L BA, CA, A10 WRIT/WRITA BA, RA ACT L BA, A10 PRE/PREA X AREF/SELF L Op-Code MRS/EMRS - 19 - W9425G6EB ACTION NOP NOP ILLEGAL ILLEGAL Row activating NOP Refresh or Self refresh Mode register accessing NOP NOP Begin read: Determine AP Begin write: Determine AP ILLEGAL Precharge ILLEGAL ...
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... BA, CA, A10 READ/READA L BA, CA, A10 WRIT/WRITA H BA, RA ACT L BA, A10 PRE/PREA H X AREF/SELF L Op-Code MRS/EMRS - 20 - W9425G6EB ACTION NOTES Continue burst to end Continue burst to end ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue burst to end Continue burst to end ILLEGAL ILLEGAL ILLEGAL ILLEGAL ...
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... X ACT/PRE/PREA X AREF/SELF/MRS/EMRS X DSL X NOP L X BST X READ/WRIT ACT/PRE/PREA/ARE X F/SELF/MRS/EMRS W9425G6EB ACTION NOTES NOP -> Row active after t WR NOP -> Row active after t WR ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP -> Enter precharge after t WR NOP -> Enter precharge after t WR ILLEGAL ...
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... Refer to Function Truth Table Enter Power down Enter Power down ILLEGAL ILLEGAL ILLEGAL Power down Refer to Function Truth Table - 22 - W9425G6EB ACTION NOTES XSNR XSNR IS Publication Release Date:Feb. 12, 2009 Revision A02 ...
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... IDLE PDEX ACT PDEX PD ROW ACTIVE Write Read Read A Write A Read A PRE PRE PRE PRE CHARGE PRE - 23 - W9425G6EB SELF REFRESH SREFX AUTO REFRESH PD POWER DOWN BST Read Read Read Read A Read A Automatic Sequence Command Sequence Publication Release Date:Feb. 12, 2009 Revision A02 ...
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... MIN. TYP. 2.3 2.5 2.3 2 DDQ V - 0.04 V REF REF V + 0.15 REF -0.3 -0.3 0. 0.31 REF - 0 0.2 DDQ 0.2 DDQ +1.5V with a pulse width < W9425G6EB RATING UNIT -0 +0.5 V DDQ - °C - °C -55 ~ 150 °C 260 ° MAX. UNIT NOTES 2.7 V 2 ...
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... OUT (DC) DDQ OUT MIN. 1.5 1.5 3.5 < Pin 0V < V < DD REF IN < OUT DDQ , min. V REF TT , max REF TT , min. V REF min. V REF TT , max REF W9425G6EB DELTA MAX. (MAX.) 2.5 0.5 2.5 0.25 4.5 0.5 UNIT MIN. MAX µ µA V +0. -0. - ...
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... max for DQ, DQS and DM IL min min min; CK min; One Bank Active-Precharge; IH min; = 0mA = t min RC RFC = 0mA W9425G6EB MAX. UNIT NOTES -5 -6I 110 110 150 150 180 170 180 170 190 ...
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... -0.7 0.7 -0.6 0.6 0.4 0.45 0.55 0.45 0.55 min -0.5 0.9 1.1 0.4 0.6 0.4 0.4 1.75 0.35 0.35 0.2 0.2 0 0.25 0.4 0.6 0.72 1.25 0.6 0.6 0.7 0.7 2.2 0.7 -0.7 0.7 0.5 1 200 7.8 10 Publication Release Date:Feb. 12, 2009 - 27 - W9425G6EB -6I UNIT NOTES MIN. MAX 100000 7 -0.7 0.7 16 -0.6 0.6 16 0.4 0.45 0. 0.45 0.55 Min -0.5 0.9 1 0.4 0.6 0.45 ...
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... DDQ system supply for signal termination resistors is expected to be set TT . REF and V .Transition (rise and fall) of input signals have a fixed IH min(AC) IL max(AC) contains more than one decimal place, the result is rounded W9425G6EB VALUE 0.31 IH REF 0.31 IL REF V 0 ...
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... These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. (23) Slew Rate is measured between ICK ICK V V ISO(min) ISO(max) (ac) and V (ac W9425G6EB ICK ID(AC) Publication Release Date:Feb. 12, 2009 Revision A02 ...
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... +75 0 +150 0 Δt Δ +50 0 +100 0 TYPICAL MINIMUM RANGE (V/nS) (V/nS) 1.2 ~ 2.5 0.7 1.2 ~ 2.5 0 W9425G6EB DDR333 UNIT NOTES MIN. MAX. 0.5 4.0 V/ UNIT NOTES UNIT NOTES UNIT NOTES MAXIMUM ...
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... Verified under typical conditions for qualification purposes. f. TSOP II package devices only. g. Only intended for operation up to 266 Mbps per pin 320 mV ± 250 mV) DDQ /2 + 320 mV ± 250 mV) DDQ = nominal, typical process DDQ = minimum, slow-slow process DDQ = maximum, fast-fast process DDQ Publication Release Date:Feb. 12, 2009 - 31 - W9425G6EB Revision A02 ...
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... DQ, DM, and DQS slew IL(AC) IH(DC) IL(DC) and t in the case where the I/O slew rate is below 0.5 V/nS. The W9425G6EB , similarly for rising transitions. , similarly for rising transitions. and IH(AC) IL(AC) Publication Release Date:Feb. 12, 2009 Revision A02 of 100 IH(DC) ...
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... CLK CLK Refer to the Command Truth Table W9425G6EB IH(AC) V IL(AC Publication Release Date:Feb. 12, 2009 Revision A02 ...
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... IS IH READ CMD ADD Col CAS Latency = 2 Hi-Z DQS Output Hi-Z (Data) CAS Latency = 3 Hi-Z DQS Output Hi-Z (Data) Notes: The correspondence of LDQS, UDQS to DQ. (W9425G6EB) LDQS DQ0~7 UDQS DQ8~ DQSCK t DQSCK t RPRE Preamble DQSQ QH QA0 QA1 DA0 DA1 t AC ...
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... DA0 DA1 DA2 DA3 DA0 DA1 DA2 DA3 DSH DSS DSH DSS DQSL DQSH WPST DQSH Postamble DA0 DA1 DA2 DA3 DA0 DA1 DA2 DA3 - 35 - W9425G6EB Publication Release Date:Feb. 12, 2009 Revision A02 ...
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... DM, DATA MASK (W9425G6EB ...
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... Reserved A11 "0" A12 "0" BA0 "0" Mode Register Set or Extended Mode "0" BA1 Register Set * "Reserved" should stay "0" during MRS cycle. W9425G6EB t MRD NEXT CMD Burst Length Sequential Reserved ...
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... MRD NEXT CMD DLL Switch A0 Enable 0 Disable Buffer Strength 0 0 100% Strength 1 0 60% Strength 0 1 Reserved 1 1 30% Strength BA0 MRS or EMRS BA1 Regular MRS cycle 0 0 Extended MRS cycle Reserved 1 1 Publication Release Date:Feb. 12, 2009 - 38 - W9425G6EB Revision A02 ...
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... In this case, the internal precharge operation begin after BL/2 cycle from READA command. AP Represents the start of internal precharging. The Read with Auto-precharge command cannot be interrupted by any other command RAS READA READA READA W9425G6EB tRP ACT ACT ACT ...
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... The Read with Auto-precharge command cannot be interrupted by any other command. – (BL/2) × t RAS (min RAS READA Q0 Q1 READA READA W9425G6EB t RP ACT AP AP ACT Q3 AP ACT (min) has command. RAS Publication Release Date:Feb. 12, 2009 Revision A02 ...
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... CMD DQS BL=8 WRITA CMD DQS The Write with Auto-precharge command cannot be interrupted by any other command. AP Represents the start of internal precharging . t DAL AP t DAL W9425G6EB ACT ACT t DAL AP ACT Publication Release Date:Feb. 12, 2009 Revision A02 ...
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... READ A READ RCD CCD CCD COl,Add,A Col,Add,B Col,Add,C BST CAS Latency CAS Latency W9425G6EB READ C READ D READ CCD CCD Col,Add,D Col,Add,E QA0 QA1 QB0 QB1 QC0 Publication Release Date:Feb. 12, 2009 Revision A02 ...
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... C AS Latency = Latency = BST WRIT Latency Latency W9425G6EB Publication Release Date:Feb. 12, 2009 Revision A02 ...
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... COl. Add. A Col.Add.B Col. Add. C DA0 DA1 DB0 READ t WTR Data masked by READ command, DQS input ignored W9425G6EB WRIT D WRIT CCD CCD Col. Add. D Col. Add. E DB1 DC0 DC1 DD0 DD1 Publication Release Date:Feb. 12, 2009 ...
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... Write Interrupted by Precharge ( CLK CLK WRIT CMD DQS READ t WTR D2 D3 Data must be masked by DM PRE ACT Data must be Data masked by PRE command, masked by DM DQS input ignored W9425G6EB Publication Release Date:Feb. 12, 2009 Revision A02 ...
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... RAS(a) RP(a) t RCD(b) t RAS(b) Preamble CL(a) APa t RC(b) t RC(a) ACTb READAa READAb t RCD(a) t RAS(a) t RCD(b) t RAS(b) Preamble CL(a) CL(b) Q0a Q1a APa - 46 - W9425G6EB t RRD ACTa ACTb t RP(b) Postamble Preamble Postamble CL(b) Q0a Q1a Q0b Q1b APb t RRD ACTa ACTb t RP(a) t RP(b) Postamble Q2a Q3a Q0b Q1b Q2b Q3b APb Publication Release Date:Feb ...
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... W9425G6EB EAD READ D(c) t RAS( (d) t RAS(d) Pream ble Postam ble ...
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... Minmum 2 clocks required before changing frequency AREF NOP t RFC Entry NOP Frequency Change Occurs here Stable new clock before power down exit - 48 - W9425G6EB AREF CMD NOP t RFC t IS Exit NOP CMD NOP DLL NOP NOP NOP CMD RESET t IS 200 clocks Publication Release Date:Feb ...
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... SELF t RP Entry SELF Entry Note: If the clock frequency is changed during self refresh mode, a DLL reset is required upon exit SELEX Exit t XSNR t XSRD SELFX NOP ACT NOP READ Exit Publication Release Date:Feb. 12, 2009 - 49 - W9425G6EB NOP CMD NOP Revision A02 ...
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... Note: Solder ball is ψ0.45mm before reflow “ ＂ 0. 0 ψ0.15 M Detail A “ ＂ S ψ0. W9425G6EB C 0.1 Dimension in inch Dimension in mm Symbol Min Nom Max Min Nom Max A --- --- 0.051 --- --- A1 0.01 --- 0.016 0.25 --- 0.016 --- 0.02 0.40 --- ψb D 0.507 0.512 0.515 12.9 13.0 D1 --- 0.433 --- --- 11 ...
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... Winbond customers using or selling these products for use in such applications their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. PAGE All Formally data sheet 4, 5, 16, Add 30% driver strength support and -6I grade parts 24~27, 30, 38 Important Notice - 51 - W9425G6EB DESCRIPTION Publication Release Date:Feb. 12, 2009 Revision A02 ...