lh28f016sct-zr Sharp Microelectronics of the Americas, lh28f016sct-zr Datasheet
lh28f016sct-zr
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... P S RODUCT PECIFICATION LH28F016SCT-ZR Flash Memory 16Mbit (2Mbitx8) (Model Number: LHF16CZR) Spec. Issue Date: October 14, 2004 Spec No: EL16X101 Integrated Circuits Group ...
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Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. When using the products covered herein, please observe ...
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INTRODUCTION ................................................... 3 1.1 New Features...................................................... 3 1.2 Product Overview ................................................ 3 2.0 PRINCIPLES OF OPERATION ............................. 7 2.1 Data Protection ................................................... 8 3.0 BUS OPERATION................................................. 8 3.1 Read ................................................................... 8 3.2 Output Disable .................................................... 8 3.3 Standby ............................................................... ...
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... Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F016SCT-ZR offers three levels of protection: absolute protection with V GND, selective hardware block locking, or flexible software block locking. These alternatives give designers ultimate control of their code security needs. The LH28F016SCT-ZR is manufactured on SHARP’ ...
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... Both devices share a compatible pinout, status register, and software command similarities enable a clean upgrade from the 28F008SA to LH28F016SCT-ZR. When upgrading important to note the following differences: •Because of new feature support, the two devices have different device codes. This allows for software optimization. •V has been lowered from 6 ...
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Individual block locking uses a combination of bits, thirty-two block lock-bits and a master lock-bit, to lock and unlock blocks. Block lock-bits gate block erase and byte write operations, while the master lock-bit gates block lock-bit modification. configuration operations (Set ...
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Output Buffer Y Input Decoder Buffer X Address Latch Decoder Address Counter Figure 1. Block Diagram ...
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... INPUT 0 20 are internally latched during a write cycle. DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles; outputs INPUT/ data during memory array, status register, and identifier code read cycles. Data pins float DQ - OUTPUT to high-impedance when the chip is deselected or outputs are disabled. Data is internally latched during a write cycle. CHIP ENABLE: Activates the device’ ...
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... PRINCIPLES OF OPERATION The LH28F016SCT-ZR SmartVoltage Flash memory includes an on-chip WSM to manage block erase, byte write, and lock-bit configuration functions. It allows for: 100% TTL-level control inputs, fixed power supplies during block erasure, byte write, and lock-bit configuration, and minimal processor overhead with RAM-Like interface timings ...
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... BUS OPERATION The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 Read Information can be read from any block, identifier codes, or status register independent of the V voltage ...
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... Lock) or block within the device (Block Lock locked. The Clear Block Lock-Bits command requires the command and address within the device. The CUI does not occupy an addressable memory location written when WE# and CE# are active. The address and data needed to execute a command are latched on the rising edge of WE# or CE# (whichever goes high first) ...
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... ≤V , memory contents can be read, but not altered. PP PPLK or V PPLK PPH1/2 Address V DQ RY/BY OUT X X High High High Z V See X Note 5 ...
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... IA=Identifier Code Address: see Figure 4. BA=Address within the block being erased or locked. WA=Address of memory location to be written. 3. SRD=Data read from status register. See Table 7 for a description of the status register bits. WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first) ...
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... Future Use NOTE selects the specific block lock configuration code to be read. See Figure 4 for the device identifier code memory map. LHF16CZR 4.3 Read Status Register Command The status register may be read to determine when a block erase, byte write, or lock-bit configuration is complete and whether the operation completed successfully ...
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... The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and ...
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... The only other valid commands while byte write is suspended are Read Status Register and Byte Write Resume. After Byte Write Resume command is written to the flash memory, the WSM will continue the byte write process. Status register bits SR.2 and SR.7 will automatically clear and RY/BY# will return to V ...
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Clear Block Lock-Bits Command All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. With the master lock-bit not set, block lock-bits can be cleared using only the Clear Block Lock-Bits command. If the master ...
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WSMS ESS ECLBS SR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE AND CLEAR LOCK-BITS ...
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Start Write 20H, Block Address Write D0H, Block Address Read Status Register Suspend Block No 0 Suspend SR.7= Block Erase Yes 1 Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 ...
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Start Write 40H, Address Write Byte Data and Address Read Status Register No 0 Suspend SR.7= Byte Write Yes 1 Full Status Check if Desired Byte Write Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 SR.3= V ...
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Start Write B0H Read Status Register 0 SR. SR.6= Block Erase Completed 1 Read or Read Byte Write Byte Write ? Read Array Data Byte Write Loop No Done? Yes Write D0H Write FFH Block Erase Resumed Read ...
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Start Write B0H Read Status Register 0 SR. SR.2= Byte Write Completed 1 Write FFH Read Array Data Done No Reading Yes Write D0H Write FFH Read Array Data Byte Write Resumed Figure 8. Byte Write Suspend/Resume Flowchart ...
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Start Write 60H, Block/Device Address Write 01H/F1H, Block/Device Address Read Status Register 0 SR.7= 1 Full Status Check if Desired Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 SR.3= V Range Error ...
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Start Write 60H Write D0H Read Status Register 0 SR.7= 1 Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 SR.3= V Range Error SR.1= Device Protect ...
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... DESIGN CONSIDERATIONS 5.1 Three-Line Output Control The device will often be used in large memory arrays. SHARP provides three control accommodate multiple memory Three-line control provides for: a. Lowest possible memory power dissipation. b. Complete assurance that data bus contention will not occur. To use these control inputs efficiently, an address decoder should enable CE# while OE# should be connected to all memory devices and the system’ ...
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... After block erase, byte write, or lock-bit configuration, even after V transitions down must be placed in read array mode via the Read Array command if subsequent access to the memory array is desired. 5.6 Power-Up/Down Protection The device is designed to offer protection against accidental block erasure, byte writing, or lock-bit ...
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ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings* Operating Temperature During Read, Block Erase, Byte Write and Lock-Bit Configuration ...........0°C to +70°C Temperature under Bias............... -10°C to +80°C Storage Temperature........................ -65°C to +125°C Voltage On Any Pin (except ...
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AC INPUT/OUTPUT TEST CONDITIONS 2.7 INPUT 0.0 AC test inputs are driven at 2.7V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.35V. Input rise and fall times (10% ...
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DC CHARACTERISTICS Sym. Parameter Notes Typ. I Input Load Current LI I Output Leakage Current Standby Current CCS Deep Power-Down CCD CC Current I V Read Current CCR Byte Write ...
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Sym. Parameter Notes Min. V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage 3 Output High Voltage 3,7 OH1 (TTL) V Output High Voltage 3,7 OH2 (CMOS Lockout during 4,7 PPLK ...
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AC CHARACTERISTICS - READ-ONLY OPERATIONS Versions Sym. Parameter t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV t RP# High to Output Delay PHQV t OE# to Output Delay GLQV t ...
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Versions Sym. Parameter t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV t RP# High to Output Delay PHQV t OE# to Output Delay GLQV t CE# to Output in Low ...
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Standby Address Selection V IH ADDRESSES( CE#( OE#( WE#( HIGH Z DATA(D/Q) (DQ - PHQV V ...
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AC CHARACTERISTICS - WRITE OPERATION Versions Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to WE# Going Low PHWL t CE# Setup to WE# Going Low ELWL t WE# Pulse Width WLWH t Address Setup to ...
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Versions Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to WE# Going Low PHWL t CE# Setup to WE# Going Low ELWL t WE# Pulse Width WLWH t RP# V Setup to WE# Going High PHHWH ...
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V IH ADDRESSES( CE#( OE#( WE#( High Z DATA(D/ RY/BY#( RP#( ...
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ALTERNATIVE CE#-CONTROLLED WRITES Versions Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to CE# Going Low PHEL t WE# Setup to CE# Going Low WLEL t CE# Pulse Width ELEH t Address Setup to CE# Going ...
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Versions Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to CE# Going Low PHEL t WE# Setup to CE# Going Low WLEL t CE# Pulse Width ELEH t RP# V Setup to CE# Going High PHHEH ...
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V IH ADDRESSES( WE#( OE#( CE#( High Z DATA(D/ RY/BY#( RP#( ...
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RESET OPERATIONS V OH RY/BY#( RP#( RY/BY#( RP#( (B)Reset During Block Erase, Byte Write, or Lock-Bit Configuration 2.7V/3.3V/ RP#(P) ...
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BLOCK ERASE, BYTE WRITE AND LOCK-BIT CONFIGURATION PERFORMANCE Sym. Parameter t WHQV1 Byte Write Time t EHQV1 Block Write Time t WHQV2 Block Erase Time t EHQV2 t WHQV3 Set Lock-Bit Time t EHQV3 t WHQV4 Clear Block Lock-Bits ...
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... S = Regular Block Power Supply Type C = SmartVoltage Technology Operating Temperature blank = 0°C ~ +70° -40°C ~ +85°C V Option Order Code 1.35V I/O Levels 1 LH28F016SCT-ZR LH28F016SC-L150 LH28F016SC-L120 LH28F016SC-L100 LH28F016SC-L90 LHF16CZR - ( ) H T Access Speed (ns) 90ns(5V,30pF), 100ns(5V), 120ns(3.3V), 150ns(2.7V) Package T = 40-Lead TSOP R = 40-Lead TSOP(Reverse Bend 48-Ball CSP Valid Operational Combinations =2 ...
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A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate ...
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A-1.1.1 Rise and Fall Time Symbol t V Rise Time Input Signal Rise Time R t Input Signal Fall Time F NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the device ...
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A-1.2 Glitch Noises Do not input the glitch noises which are below V as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a). Input Signal V (Min (Max.) IL Input Signal (a) ...
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... A-2 RELATED DOCUMENT INFORMATION Document No. AP-001-SD-E Flash Memory Family Software Drivers AP-006-PT-E Data Protection Method of SHARP Flash Memory RP#, V AP-007-SW-E NOTE: 1. International customers should contact their local SHARP or distribution sales office. (1) Document Name Electric Potential Switching Circuit PP iv Rev. 1.10 ...
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... ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED event will SHARP be liable any way responsible, for any incidental or consequential economic or property damage. NORTH AMERICA SHARP Microelectronics of the Americas 5700 NW Pacific Rim Blvd. Camas, WA 98607, U.S.A. Phone: (1) 360-834-2500 ...