hyb39s256400

Manufacturer Part Numberhyb39s256400
Description256 Mbit Synchronous Dram
ManufacturerInfineon Technologies Corporation
hyb39s256400 datasheet
 
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256 MBit Synchronous DRAM
High Performance:
-6
-7
-7.5
-8
Units
fCK
166
143
133
125
MHz
tCK3
6
7
7.5
8
ns
tAC3
5
5.4
5.4
6
ns
tCK2
7.5
7.5
10
10
ns
tAC2
5.4
5.4
6
6
ns
Fully Synchronous to Positive Clock Edge
0 to 70 °C operating temperature
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2 & 3
Programmable Wrap Sequence: Sequential
or Interleave
Programmable Burst Length:
1, 2, 4, 8 and full page
Multiple Burst Read with Single Write
Operation
Automatic
and
Controlled
Precharge
Command
The HYB39S256400/800/160DT(L) are four bank Synchronous DRAM’s organized as 4 banks x
16MBit x4, 4 banks x 8MBit x8 and 4 banks x 4Mbit x16 respectively. These synchronous devices
achieve high speed data transfer rates for CAS-latencies by employing a chip architecture that
prefetches multiple bits and then synchronizes the output data to a system clock. The chip is
fabricated with INFINEON’s advanced 0.14 µm 256MBit DRAM process technology.
The device is designed to comply with all industry standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur
at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is
possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single
3.3V +/- 0.3V power supply. All 256Mbit components are available in TSOPII-54 and TFBGA-54
packages.
INFINEON Technologies
HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
Data Mask for Read / Write control (x4, x8)
Data Mask for byte control (x16)
Auto Refresh (CBR) and Self Refresh
Power Down and Clock Suspend Mode
8192 refresh cycles / 64 ms (7,8 µs)
Random Column Address every CLK
( 1-N Rule)
Single 3.3V +/- 0.3V Power Supply
LVTTL Interface versions
Plastic Packages:
P-TSOPII-54 400mil width (x4, x8, x16)
Chipsize Packages:
54 ball TFBGA (12 mm x 8 mm)
-6 parts for PC166 3-3-3 operation
-7 parts for PC133 2-2-2 operation
-7.5 parts for PC133 3-3-3 operation
-8 parts for PC100 2-2-2 operation
1
2002-04-23

hyb39s256400 Summary of contents

  • Page 1

    ... Precharge • Command The HYB39S256400/800/160DT(L) are four bank Synchronous DRAM’s organized as 4 banks x 16MBit x4, 4 banks x 8MBit x8 and 4 banks x 4Mbit x16 respectively. These synchronous devices achieve high speed data transfer rates for CAS-latencies by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated with INFINEON’ ...

  • Page 2

    ... CAS Column Address Strobe WE Write Enable A0-A12 Address Inputs BA0, BA1 Bank Select INFINEON Technologies HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM Package Description P-TSOP-54-2 (400mil) 166MHz 4B x 16M x 4 SDRAM P-TSOP-54-2 (400mil) 143MHz 4B x 16M x 4 SDRAM P-TSOP-54-2 (400mil) 133MHz 4B x 16M x 4 SDRAM ...

  • Page 3

    ... TSOPII-54 (400 mil x 875 mil, 0.8 mm pitch) INFINEON Technologies HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM N.C. DQ7 DQ15 SSQ SSQ SSQ 51 N.C. N.C. ...

  • Page 4

    ... VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC NC VSS DQM CLK CKE A12 A11 VSS A5 A4 INFINEON Technologies HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM VDDQ DQ0 VDD B VSSQ DQ2 DQ1 C VDDQ DQ4 DQ3 D VSSQ DQ6 DQ5 E VDD LDQM DQ7 F ...

  • Page 5

    ... ffe ffe Block Diagram for 64M x 4 SDRAM ( addressing) INFINEON Technologies HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM ...

  • Page 6

    ... Bit x 8 Bit Input Buffer Output Buffer DQ0 - DQ7 Block Diagram for 32M x 8 SDRAM ( addressing) INFINEON Technologies HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM Row Addresses A0 - A12, BA0, BA1 Row Address Refresh Counter Buffer Row Row Decoder ...

  • Page 7

    ... Bank 1 8192 x 512 8192 x 512 x 16 Bit x 16 Bit Input Buffer Output Buffer DQ0 - DQ15 Block Diagram for 16M x16 SDRAM ( addressing) INFINEON Technologies HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM Row Addresses A0 - A12, BA0, BA1 Row Address Refresh Counter Buffer Row Row ...

  • Page 8

    ... Bank Select Inputs. Bank address inputs selects which of the four banks a command applies to. DQx Input Level – Data Input/Output pins operate in the same manner as on Output conventional DRAMs. INFINEON Technologies HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM CAn = CA9 (Page Length = 1024 bits) CAn = CA8 (Page Length = 512 bits) 8 2002-04-23 ...

  • Page 9

    ... Supply – – Power and ground for the input buffers and the core logic Supply – – Isolated power supply and ground for the output buffers to DDQ V provide improved noise immunity. SSQ INFINEON Technologies HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM 9 2002-04-23 ...

  • Page 10

    ... This is the state of the banks designated by BA0, BA1 signals. 4. Power Down Mode can not be entered in a burst cycle. When this command asserted in the burst mode cycle device is in clock suspend mode. INFINEON Technologies HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM CKE DQM BA0 ...

  • Page 11

    ... Reserved Reserved Reserved INFINEON Technologies HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM Address Bus (Ax) CAS Latency BT Burst Length Mode Register (Mx) Burst Type M3 Type 0 Sequential 1 Interleave Burst Length Length Sequential ...

  • Page 12

    ... Full page burst operation is only possible using the sequential burst type and page length is a function of the I/O organization and column addressing. Full page burst operation does not self INFINEON Technologies HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM , from the RAS timing used to define either ...

  • Page 13

    ... The mode restores word line after the refresh and no external precharge command is necessary. A minimum tRC time is required between two automatic refreshes in a burst refresh mode. The same rule applies to any access command after the automatic refresh operation. INFINEON Technologies HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM Interleave Burst Addressing (decimal ...

  • Page 14

    ... CAS latency = 2 and two clocks before the last data out for CAS latency = 3. Writes require a time delay twr (“write recovery time” clocks minimum from the last data out to apply the precharge command. INFINEON Technologies HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM ). 14 ...

  • Page 15

    ... Input capacitance (CLK) Input capacitance (A0-A12, BA0,BA1,RAS, CAS, WE, CS, CKE, DQM) Input / Output capacitance (DQ) Note: Capacitance values are shown for TSOP-54 packages. Capacitance values for TFBGA packages are lower by 0.5 pF. INFINEON Technologies HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM 0 Bank 0 1 Bank 1 0 Bank 2 1 ...

  • Page 16

    ... SS 2. Vih may overshoot 2.0 V for pulse width of < 4ns with 3.3V. Vil may undershoot to -2.0 V for pulse DDQ width < 4.0 ns with 3.3V. Pulse width measured at 50% points with amplitude reference. INFINEON Technologies HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM Symbol Limit Values min. max – 1.0 4 ...

  • Page 17

    ... These parameters are measured with continuous data stream during read access and all DQ toggling. CL=3 and BL=4 is assumed and the VDDQ current is excluded “burst refresh” 7.8 µs “distributed refresh”. RFC RFC(min) RFC INFINEON Technologies HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM -6 -7 -7.5 -8 Symb. max. , IDD1 100 ...

  • Page 18

    ... SB Common Parameters Row to Column Delay Time t RCD Row Precharge Time t RP Row Active Time t RAS Row Cycle Time t RC INFINEON Technologies HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM Limit Values -6 -7 -7.5 PC166- PC133- PC133- PC100- 333 222 333 min. max. min. max. min. ...

  • Page 19

    ... DQZ Write Cycle Last Data Input to Precharge t WR (Write without AutoPrecharge) Last Data Input to Activate t DAL,min (Write with AutoPrecharge) DQM Write Mask Latency t DQW INFINEON Technologies HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM Limit Values -6 -7 -7.5 PC166- PC133- PC133- PC100- 333 222 333 min. ...

  • Page 20

    ... When a Write command with AutoPrecharge has been issued, a time of tdal(min) has be fullfilled before the next Activate Command can be applied. For each of the terms, if not already an integer, round up to the next highest integer. tck is equal to the actual system clock time. INFINEON Technologies HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM V = 0.4 V and ...

  • Page 21

    ... Index Marking 1) Does not include plastic or metal protrusion of 0.15 max per side 2) Does not include plastic protrusion of 0.25 max per side 3) Does not include dambar protrusion of 0.13 max per side INFINEON Technologies HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM 2) 10.16 ±0.13 0.5 ±0.1 11.76 ±0.2 0.1 54x 0.2 54x M ...

  • Page 22

    ... Package Outlines- TFBGA TFBGA-54 package ( mm, 54 balls) INFINEON Technologies HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM 22 2002-04-23 ...