hyb39s256400 Infineon Technologies Corporation, hyb39s256400 Datasheet - Page 9

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hyb39s256400

Manufacturer Part Number
hyb39s256400
Description
256 Mbit Synchronous Dram
Manufacturer
Infineon Technologies Corporation
Datasheet

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Pin
DQM
LDQM
UDQM
V
V
V
V
INFINEON Technologies
DD
SS
DDQ
SSQ
Type
Input
Supply –
Supply –
Signal Polarity Function
Pulse
Active
High
The Data Input/Output mask places the DQ buffers in a
high impedance state when sampled high. In Read mode,
DQM has a latency of two clock cycles and controls the
output buffers like an output enable. In Write mode, DQM
has a latency of zero and operates as a word mask by
allowing input data to be written if it is low but blocks the
write operation if DQM is high.
One DQM input is present in x4 and x8 SDRAMs, LDQM
and UDQM controls the lower and upper bytes in x16
SDRAMs.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to
provide improved noise immunity.
9
HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
2002-04-23

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