hyb18t512160b2fl-5 Qimonda, hyb18t512160b2fl-5 Datasheet
hyb18t512160b2fl-5
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hyb18t512160b2fl-5 Summary of contents
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... We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc@qimonda.com qag_techdoc_A4, 4.20, 2008-01-25 10062006-YPTZ-CDR7 HY[B/I]18T512[40/80/16]0B2[C/F](L) 512-Mbit Double-Data-Rate-Two SDRAM ...
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Overview This chapter gives an overview of the 512-Mbit Double-Data-Rate-Two SDRAM product family and describes its main characteristics. 1.1 Features The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features: ± • 1.8 V 0.1 V Power Supply ± 1.8 ...
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QAG Speed Code DRAM Speed Grade DDR2 CAS-RCD-RP latencies f Max. Clock Frequency CL3 CK3 f CL4 CK4 f CL5 CK5 f CL6 CK6 t Min. RAS-CAS-Delay RCD t Min. Row Precharge Time RP t Min. Row Active Time RAS ...
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... HYB18T512800B2FL-3.7 DDR2-533C ×16 HYB18T512160B2FL-3.7 DDR2-533C ×8 HYB18T512800B2F-3.7 DDR2-533C ×4 HYB18T512400B2F-3.7 DDR2-533C ×16 HYB18T512160B2F-3.7 DDR2-533C DDR2-400B( 3-3-3 ) ×16 HYB18T512160B2FL-5 DDR2-400B Rev. 1.40, 2008-03 10062006-YPTZ-CDR7 HY[B/I]18T512[40/80/16]0B2[C/F](L) 512-Mbit Double-Data-Rate-Two SDRAM Ordering Information for RoHS Compliant Products CAS-RCD-RP Clock (MHz) Package 2)3)4) Latencies 6-6-6 400 PG-TFBGA-60 6-6-6 400 ...
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... DDR2-400B ×8 HYI18T512800B2F-5 DDR2-400B 1) For detailed information regarding product type of Qimonda please see chapter "Product Nomenclature" of this data sheet. 2) CAS: Column Address Strobe 3) RCD: Row Column Delay 4) RP: Row Precharge 5) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003 ...
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Product Type Org. Standard Temperature Range (0 °C - +95 °C) DDR2-800E( 6-6-6 ) ×4 HYB18T512400B2C-2.5 ×8 HYB18T512800B2C-2.5 ×16 HYB18T512160B2C-2.5 DDR2-800D( 5-5-5 ) ×4 HYB18T512400B2C-25F ×8 HYB18T512800B2C-25F ×16 HYB18T512160B2C-25F DDR2-667D( 5-5-5 ) ×4 HYB18T512400B2C-3S ×8 HYB18T512800B2C-3S ×16 HYB18T512160B2C-3S DDR2-667C( ...
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... HYI18T512160B2C-3.7 DDR2-400B( 3-3-3 ) ×4 HYI18T512400B2C-5 ×8 HYI18T512800B2C-5 ×16 HYI18T512160B2C-5 1) For detailed information regarding product type of Qimonda please see chapter "Product Nomenclature" of this data sheet. 2) CAS: Column Address Strobe 3) RCD: Row Column Delay 4) RP: Row Precharge Rev. 1.40, 2008-03 10062006-YPTZ-CDR7 512-Mbit Double-Data-Rate-Two SDRAM Speed ...
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Configuration This chapter contains the chip configuration. 2.1 Configuration for TFBGA-60 The chip configuration of a DDR2 SDRAM is listed by function in explained in Table 5 and Table 6 respectively. The ball numbering for the FBGA package is ...
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Ball# Name Ball Type Data Signals ×4 /×8 Organizations C8 DQ0 I/O C2 DQ1 I/O D7 DQ2 I/O D3 DQ3 I/O D1 DQ4 I/O D9 DQ5 I/O B1 DQ6 I/O B9 DQ7 I/O Data Strobe ×4 /×8 Organizations B7 DQS ...
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Abbreviation Description I Standard input-only ball. Digital levels O Output. Digital levels I/O I bidirectional input/output signal AI Input. Analog levels PWR Power GND Ground NC Not Connected Abbreviation Description SSTL Serial Stub Terminated Logic (SSTL_18) LV-CMOS Low ...
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V V Note: and are power and ground for the DLL. DDL SSDL V are isolated on the device. SSQ Rev. 1.40, 2008-03 10062006-YPTZ-CDR7 HY[B/I]18T512[40/80/16]0B2[C/F](L) 512-Mbit Double-Data-Rate-Two SDRAM Configuration for ×4 Components, TFBGA-60 (top view connected to ...
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Notes 1. RDQS / RDQS are enabled by EMRS(1) command RDQS / RDQS is enabled, the DM function is disabled 3. When enabled, RDQS & RDQS are used as strobe signals during reads and are ...
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Configuration for TFBGA-84 The chip configuration of a DDR2 SDRAM is listed by function in columns are explained in Table 8 and Table 9 Ball# Name Ball Type Clock Signals ×16 Organization ...
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Ball# Name Ball Type Data Signals ×16 Organization G8 DQ0 I/O G2 DQ1 I/O H7 DQ2 I/O H3 DQ3 I/O H1 DQ4 I/O H9 DQ5 I/O F1 DQ6 I/O F9 DQ7 I/O C8 DQ8 I/O C2 DQ9 I/O D7 DQ10 ...
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Ball# Name Ball Type Not Connected ×16 Organization A2, E2, L1, R3 R7, R8 Other Balls ×16 Organization K9 ODT I Rev. 1.40, 2008-03 10062006-YPTZ-CDR7 512-Mbit Double-Data-Rate-Two SDRAM Buffer Function Type – Not Connected SSTL On-Die Termination Control ...
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Abbreviation Description I Standard input-only ball. Digital levels. O Output. Digital levels. I/O I bidirectional input/output signal. AI Input. Analog levels. PWR Power GND Ground NC Not Connected Abbreviation Description SSTL Serial Stub Terminated Logic (SSTL_18) LV-CMOS Low ...
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Notes 1. UDQS/UDQS is data strobe for DQ[15:8], LDQS/LDQS is data strobe for DQ[7:0] 2. LDM is the data mask signal for DQ[7:0], UDM is the data mask signal for DQ[15: and are power and ground for ...
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Addressing This chapter describes the DDR2 addressing. Configuration 128 Bank Address BA[1:0] Number of Banks 4 Auto Precharge A10 / AP Row Address A[13:0] Column Address A11, A[9:0] Number of Column Address Bits 11 Number of ...
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Functional Description This chapter contains the functional description. 3.1 Mode Register Set (MRS) The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. 1) Field Bits Type Description BA2 16 reg. addr. Bank Address ...
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Field Bits Type Description Test Mode 0 TM Normal Mode Vendor specific test mode B CL [6:4] w CAS Latency Note: All other bit combinations are illegal. 011 100 CL ...
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Extended Mode Register EMR(1) The Extended Mode Register EMR(1) stores the data for enabling or disabling the DLL, output driver strength, additive 1) Field Bits Type Description BA2 16 reg. addr. Bank Address 2 Note: BA2 not available on ...
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Field Bits Type Description AL [5:3] w Additive Latency Note: All other bit combinations are illegal. 000 B 001 B 010 B 011 B 100 B 101 B 110 B R 6,2 w Nominal Termination Resistance of ODT TT ...
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Extended Mode Register EMR(2) The Extended Mode Registers EMR(2) and EMR(3) are reserved for future use and must be programmed when setting the mode register during initialization. 1) Field Bits Type Description BA [15:14] w Bank Adress 00 BA ...
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Extended Mode Register EMR(3) The Extended Mode Register EMR(3) is reserved for future use and all bits except BA0 and BA1 must be programmed to 0 when setting the mode register during initialization. 1) Field Bits Type Description BA2 ...
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Burst Mode Operation Burst Length Starting Address (A2 A1 A0) × × ×1 0 × ...
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Truth Tables The truth tables in this chapter summarize the commands and there signal coding to control a standard Double-Data-Rate-Two SDRAM. Function CKE Previous Cycle (Extended) Mode Register Set H Auto-Refresh H Self-Refresh Entry H Self-Refresh Exit L Single ...
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Current State CKE Previous Cycle (N-1) Power-Down L L Self Refresh L L Bank(s) Active H All Banks Idle H H Any State other than H listed above 1) Current state is the state of the DDR2 SDRAM immediately ...
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Electrical Characteristics This chapter describes the Electrical Characteristics. 5.1 Absolute Maximum Ratings Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Symbol Parameter V V Voltage on pin relative ...
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DC Characteristics Symbol Parameter V Supply Voltage DD V Supply Voltage for DLL DDDL V Supply Voltage for Output DDQ V Input Reference Voltage REF V Termination Voltage tracks with , tracks with ...
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DC & AC Characteristics DDR2 SDRAM pin timing are specified for either single ended or differential mode depending on the setting of the EMRS(1) “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The ...
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Symbol Parameter V DC input signal voltage IN(dc differential input voltage ID(dc differential input voltage ID(ac differential cross point input voltage IX(ac) AC differential cross point output voltage 0.5 × V OX(ac ...
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Output Buffer Characteristics This chapter describes the Output Buffer Characteristics. Symbol Parameter I Output Minimum Source DC Current OH I Output Minimum Sink DC Current 1 1. – ...
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Symbol Description — Output Impedance — Pull-up / Pull down mismatch — Output Impedance step size for OCD calibration S Output Slew Rate OUT V ± V ± 1 1.8 V 0.1 V DDQ ...
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Input / Output Capacitance This chapter contains the Input / Output Capacitance. Symbol Parameter CCK Input capacitance, CK and CK CDCK Input capacitance delta, CK and CK CI Input capacitance, all other input-only pins CDI Input capacitance delta, all ...
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Overshoot and Undershoot Specification This chapter contains Overshoot and Undershoot Specification. AC Overshoot / Undershoot Specification for Address and Control Pins Parameter Maximum peak amplitude allowed for overshoot area Maximum peak amplitude allowed for undershoot area V Maximum overshoot ...
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AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins Parameter Maximum peak amplitude allowed for overshoot area Maximum peak amplitude allowed for undershoot area V Maximum overshoot area above DDQ V Maximum undershoot area below SSQ AC ...
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Currents Measurement Conditions This chapter describes the Current Measurement, Specifications and Conditions. Parameter Operating Current - One bank Active - Precharge CK(IDD) RC RC(IDD) RAS RAS.MIN(IDD) Address ...
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Parameter Self-Refresh Current CKE ≤ 0.2 V; external clock off, CK and Other control and address inputs are floating, Data bus inputs are floating. Operating Bank Interleave Read Current I 1. All banks interleaving reads, = ...
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Symbol –25F –2.5 DDR2-800D DDR2-800E Max. Max DD0 DD0 DD0 DD1 DD1 I 110 109 DD1 DD2P I low power 3 3 ...
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Timing Characteristics This chapter contains speed grade definition, AC timing parameter and ODT tables. 7.1 Speed Grade Definitions Speed Grade QAG Sort Name CAS-RCD-RP latencies Parameter Symbol t Clock Period @ ...
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Speed Grade QAG Sort Name CAS-RCD-RP latencies Parameter Symbol Min. t Clock Period @ Row Active Time RAS t Row Active Time RAS ...
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Component AC Timing Parameters DRAM Component Timing Parameter by Speed Grade - DDR2–800 and DDR2–667 Parameter DQ output access time from CAS to CAS command delay Average clock high pulse width Average clock period CKE minimum ...
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Parameter Mode register set command cycle time OCD drive mode output delay DQ/DQS output hold time from DQS DQ hold skew factor Average periodic refresh Interval Auto-Refresh to Active/Auto-Refresh command period Read preamble Read postamble Active to active command period ...
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When the device is operated with input clock jitter, this parameter needs to be derated by the actual deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has t ps ...
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A maximum of eight Refresh commands can be posted to any given DDR2 SDRAM, meaning that the maximum absolute interval between any Refresh command and the next Refresh command 31) end point and begin ...
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DRAM Component Timing Parameter by Speed Grade - DDR2–533 and DDR2–400 Parameter Symbol t DQ output access time from CAS to CAS command delay CCD t CK high pulse width CH t CKE minimum high ...
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Parameter Symbol t DQ low-impedance time from CK / LZ. DQS/DQS low-impedance time from LZ.DQS MRS command to ODT update MOD delay t Mode register set command cycle MRD time t OCD drive mode ...
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Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended ...
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Rev. 1.40, 2008-03 10062006-YPTZ-CDR7 HY[B/I]18T512[40/80/16]0B2[C/F](L) 512-Mbit Double-Data-Rate-Two SDRAM Differential Input Waveform Timing - 50 Internet Data Sheet FIGURE and DS DH ...
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Rev. 1.40, 2008-03 10062006-YPTZ-CDR7 HY[B/I]18T512[40/80/16]0B2[C/F](L) 512-Mbit Double-Data-Rate-Two SDRAM Differential Input Waveform Timing - 51 Internet Data Sheet FIGURE and lS lH ...
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Jitter Definition and Clock Jitter Specification Generally, jitter is defined as “the short-term variation of a signal with respect to its ideal position in time”. The following table provides an overview of the terminology. Symbol Parameter t Average clock ...
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Symbol Parameter t Cumulative error ERR.nPER across n cycles t Average high-pulse CH.AVG width t Average low-pulse CL.AVG width t Duty-cycle jitter JIT.DUTY The following parameters are specified per their average values however understood that the following relationship ...
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Symbol Parameter Min Clock period CK.ABS t t Clock high-pulse width CH.ABS t t Clock low-pulse width CL.ABS t Example: for DDR2-667, = (0.48 x 3000ps) – 125 ps = 1315 ps = 0.438 x 3000 ps. CH.ABS.MIN ...
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ODT AC Electrical Characteristics This chapter describes the ODT AC electrical characteristics. ODT AC Characteristics and Operating Conditions for DDR2-667 , DDR2-800 Symbol Parameter / Condition t ODT turn-on delay AOND t ODT turn-on AON t ODT turn-on (Power-Down ...
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ODT AC Characteristics and Operating Conditions for DDR2-533 & DDR2-400 Symbol Parameter / Condition t ODT turn-on delay AOND t ODT turn-on AON t ODT turn-on (Power-Down Modes) AONPD t ODT turn-off delay AOFD t ODT turn-off AOF t ODT ...
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Package Outline This chapter contains the package dimension figures. Notes 1. Drawing according to ISO 8015 2. Dimensions General tolerances +/- 0.15 Rev. 1.40, 2008-03 10062006-YPTZ-CDR7 HY[B/I]18T512[40/80/16]0B2[C/F](L) 512-Mbit Double-Data-Rate-Two SDRAM Package Outline P-TFBGA-60 57 Internet Data ...
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Rev. 1.40, 2008-03 10062006-YPTZ-CDR7 HY[B/I]18T512[40/80/16]0B2[C/F](L) 512-Mbit Double-Data-Rate-Two SDRAM Package Outline PG-TFBGA-60 58 Internet Data Sheet FIGURE 12 ...
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Rev. 1.40, 2008-03 10062006-YPTZ-CDR7 HY[B/I]18T512[40/80/16]0B2[C/F](L) 512-Mbit Double-Data-Rate-Two SDRAM Package Outline P-TFBGA-84 59 Internet Data Sheet FIGURE 13 ...
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Rev. 1.40, 2008-03 10062006-YPTZ-CDR7 HY[B/I]18T512[40/80/16]0B2[C/F](L) 512-Mbit Double-Data-Rate-Two SDRAM Package Outline PG-TFBGA-84 60 Internet Data Sheet FIGURE 14 ...
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... Product Nomenclature For reference the Qimonda SDRAM component nomenclature is enclosed in this chapter. Example for Field Number 1 2 DDR2 DRAM HYB 18 Field Description 1 Qimonda Component Prefix 2 Interface Voltage [V] 3 DRAM Technology 4 Component Density [Mbit] 5 Number of I/Os 6 Product Variant 7 Die Revision 8 Package, Lead-Free Status ...
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Field Description 10 Speed Grade Rev. 1.40, 2008-03 10062006-YPTZ-CDR7 HY[B/I]18T512[40/80/16]0B2[C/F](L) 512-Mbit Double-Data-Rate-Two SDRAM Values Coding –19F DDR2–1066 6–6–6 –1.9 DDR2–1066 7–7–7 –25F DDR2–800 5–5–5 –2.5 DDR2–800 6–6–6 –3 DDR2–667 4–4–4 –3S DDR2–667 5–5–5 –3.7 DDR2–533 4–4–4 –5 DDR2–400 3–3–3 62 ...
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List of Illustrations Configuration for ×4 Components, TFBGA-60 (top view ...
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... Clock-Jitter Specifications for –667, –800 Table 43 ODT AC Characteristics and Operating Conditions for DDR2-667 , DDR2-800 . . . . . . . . . . . . . . . . . . . . . . . 55 Table 44 ODT AC Characteristics and Operating Conditions for DDR2-533 & DDR2-400 . . . . . . . . . . . . . . . . . . . . . . . 56 Table 45 Examples for Nomenclature Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 46 DDR2 Memory Components Rev. 1.40, 2008-03 10062006-YPTZ-CDR7 512-Mbit Double-Data-Rate-Two SDRAM = 000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2 001 ...
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Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system ...