hyb18t512160bf-5 Infineon Technologies Corporation, hyb18t512160bf-5 Datasheet
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HYS64T[32/64]0[01/20]HU–2.5–A HYS[64/72]T[32/64]0[00/01/20]HU–[3/3S]–A HYS[64/72]T[16/32]00[0/1]HU–3.7–A HYS[64/72]T[16/32]00[0/1]HU–5-A 240-Pin Unbuffered ...
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Edition 2005-09 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG 2005. © All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of ...
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HYS64T[32/64]0[01/20]HU–2.5–A, HYS[64/72]T[32/64]0[00/01/20]HU–[3/3S]–A, HYS[64/72]T[16/32]00[0/1]HU–3.7–A, HYS[64/72]T[16/32]00[0/1]HU–5-A Revision History: 2005-09, Rev. 1.3 Previous Version: Page Subjects (major changes since last revision) Chapter 4 SPD Codes update: Byte 49 Bit (HighT_SRFEntry) for all product types Chapter 5 Package Outlines updated Previous ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Features • 240-Pin PC2–6400, PC2–5300, PC2–4200 and PC2–3200 DDR2 SDRAM memory modules for use as main memory when installed in systems such as mobile personal computers. 16M × 64, 32M × 64, 32M × 72, 64M × 64, • 64M × 72 module organization and 16M × 16, 32M × ...
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Table 2 Performance for DDR2-533 and DDR2-400 Product Type Speed Code Speed Grade Max. Clock Frequency Min. RAS-CAS-Delay Min. Row Precharge Time Min. Row Active Time Min. Row Cycle Time Data Sheet HYS[64/72]T[16/32/64]0xxHU-[2.5/.../5]-A Unbuffered DDR2 SDRAM Modules –3.7 PC2–4200 4–4–4 ...
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... ECC modules in 32M × 72 (256MB), 64M × 72 (512MB) organization and density, intended for mounting into 240-pin connector sockets. The memory array is designed with 256-Mbit Double-Data-Rate-Two (DDR2) Synchronous DRAMs. Decoupling capacitors are mounted on the PCB board. The DIMMs feature serial presence detect based on a serial E ...
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... Table 5 Components on Modules 2) Product Type HYS64T16000HU HYS64T32001HU HYS64T64020HU HYS72T32000HU HYS72T64020HU 1) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet. 2) Green Product Data Sheet HYS[64/72]T[16/32/64]0xxHU-[2.5/.../5]-A Memory ECC Ranks Non-ECC SDRAMs 1 Non-ECC 4 1 Non-ECC 8 1 ECC ...
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Pin Configuration and Block Diagrams The pin configuration of the Unbuffered DDR2 SDRAM DIMM is listed by function in abbreviations used in columns Pin and Buffer Type are explained in numbering is depicted in Figure 1 Table 6 Pin ...
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Table 6 Pin Configuration of UDIMM (cont’d) Pin or Ball No. Name Pin Type Address Signals 71 BA0 I 190 BA1 I 54 BA2 188 A0 I 183 182 ...
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Table 6 Pin Configuration of UDIMM (cont’d) Pin or Ball No. Name Pin Type 12 DQ8 I/O 13 DQ9 I/O 21 DQ10 I/O 22 DQ11 I/O 131 DQ12 I/O 132 DQ13 I/O 140 DQ14 I/O 141 DQ15 I/O 24 DQ16 ...
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Table 6 Pin Configuration of UDIMM (cont’d) Pin or Ball No. Name Pin Type 98 DQ48 I/O 99 DQ49 I/O 107 DQ50 I/O 108 DQ51 I/O 217 DQ52 I/O 218 DQ53 I/O 226 DQ54 I/O 227 DQ55 I/O 110 DQ56 ...
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Table 6 Pin Configuration of UDIMM (cont’d) Pin or Ball No. Name Pin Type 162 CB5 I 167 CB6 I 168 CB7 I Data Strobe Bus 7 DQS0 I/O 16 DQS1 I/O 28 DQS2 ...
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Table 6 Pin Configuration of UDIMM (cont’d) Pin or Ball No. Name Pin Type Data Mask Signals 125 DM0 I 134 DM1 I 146 DM2 I 155 DM3 I 202 DM4 I 211 DM5 I 223 DM6 I 232 DM7 ...
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Table 6 Pin Configuration of UDIMM (cont’d) Pin or Ball No. Name Pin Type V 2,5,8,11,14,17,, GND SS 20,23,26,29,32, 35,38,41,44,47,, 50,65,66,79,82, 85,88,91,94,97,, 100,103,106, 109,112,115,118 ,121,124,127,, 130,133,136,139 ,142,145,148,, 151,154,157,160 ,163,166,169, 198,201,204,207 ,210,213,216,, 219,222,225,228 ,231,234,237 Other Pins 195 ODT0 I 77 ODT1 ...
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Table 7 Abbreviations for Pin Type Abbreviation I O I/O AI PWR GND NC Table 8 Abbreviations for Buffer Type Abbreviation SSTL LV-CMOS CMOS OD Data Sheet HYS[64/72]T[16/32/64]0xxHU-[2.5/.../5]-A Unbuffered DDR2 SDRAM Modules Description Standard input-only pin. Digital levels. Output. Digital ...
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VREF - Pin 001 V SS DQ0 - Pin 003 DQ1 V - Pin 005 SS DQS0 DQS0 - Pin 007 V SS DQ2 - Pin 009 DQ3 V - Pin 011 SS DQ8 DQ9 - Pin 013 V SS ...
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VREF - Pin 001 DQ0 - Pin 003 DQ1 - V - Pin 005 SS DQS0 - DQS0 - Pin 007 DQ2 - Pin 009 DQ3 - V - Pin 011 SS DQ8 - ...
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Block Diagrams Block Diagram Raw Card A UDIMM (×64, 1 Rank, ×8) Figure 3 Notes 1. DQ,DQS,DQS,DM resistors are 22 2. BAn, An, RAS, CAS, WE resistors are 5.1 3. ODT,CKE,S capacitors are All CK lines ...
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Figure 4 Block Diagram Raw Card A UDIMM (x72, 1 Rank, x8) Notes 1. DQ,DQS,DQS,DM,CB resistors are 22 2. BAn, An, RAS, CAS, WE resistors are 5.1 3. All CK lines have resistor termination between Data Sheet ...
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Figure 5 Block Diagram Raw Card C UDIMM (x64, 1 Rank, x16) Notes 1. DQ, DQS, DM resistors are 22 Data Sheet HYS[64/72]T[16/32/64]0xxHU-[2.5/.../5]-A Unbuffered DDR2 SDRAM Modules 2. BAn, An, RAS, CAS, WE resistors are 10 Ω ± ...
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Block Diagram Raw Card D UDIMM (×64, 1 Rank, ×8) Figure 6 Notes 1. DQ,DQS,DQS,DM,CB resistors are 22 2. BAn, An, RAS, CAS, WE resistors are 5.1 3. ODT,CKE,S capacitors are All CK lines have resistor termination ...
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Block Diagram Raw Card E UDIMM (×64, 2 Ranks, ×8) Figure 7 Notes 1. DQ,DQS,DQS,DM,CB resistors are 22 2. BAn, An, RAS, CAS, WE resistors are 5.1 3. ODT,CKE,S capacitors are All CK lines have resistor termination ...
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Block Diagram Raw Card F EDIMM (×72, 1 Rank, ×8) Figure 8 Notes 1. DQ,DQS,DQS,DM resistors are 22 2. BAn, An, RAS, CAS, WE resistors are 5.1 3. ODT,CKE,S capacitors are All CK lines have resistor termination ...
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Block Diagram Raw Card G UDIMM (×72, 2 Ranks, ×8) Figure 9 Notes 1. DQ,DQS,DQS,DM resistors are 22 2. BAn, An, RAS, CAS, WE resistors are 5.1 3. ODT,CKE,S capacitors are All CK lines have resistor termination ...
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Electrical Characteristics 3.1 Absolute Maximum Ratings Table 15 Absolute Maximum Ratings Parameter V Voltage on any pins relative Voltage on relative Voltage on relative to DDQ SS Storage Humidity (without ...
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Table 17 Supply Voltage Levels and DC Operating Conditions Parameter Symbol V Device Supply Voltage V Output Supply Voltage V Input Reference Voltage V SPD Supply Voltage V DC Input Logic High V DC Input Logic Low ...
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Table 19 Speed Grade Definition Speed Bins for DDR2–667 Speed Grade IFX Sort Name CAS-RCD-RP latencies Parameter Clock Frequency @ Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge ...
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AC Timing Parameters Table 21 Timing Parameter by Speed Grade - DDR2-800 Parameter DQ output access time from CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width ...
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Table 21 Timing Parameter by Speed Grade - DDR2-800 Parameter Internal Read to Precharge command delay Write preamble Write postamble Write recovery time for write without Auto-Precharge Write recovery time for write with Auto-Precharge Internal Write to Read command delay ...
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Table 22 Timing Parameter by Speed Grade - DDR2-667 Parameter DQ and DM input pulse width (each input) DQS output access time from DQS input low (high) pulse width (write cycle) DQS-DQ skew (for DQS & associated ...
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Table 22 Timing Parameter by Speed Grade - DDR2-667 Parameter Exit Self-Refresh to non-Read command Exit Self-Refresh to Read command 1) For details and notes see the relevant INFINEON component data sheet 1.8 V ± 0.1 ...
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Table 23 Timing Parameter by Speed Grade - DDR2-533 (cont’d) Parameter DQS falling edge to CK setup time (write cycle) Clock half period Data-out high-impedance time from Address and control input hold time Address and control input ...
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Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended ...
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Table 24 Timing Parameter by Speed Grade - DDR2-400 Parameter Data hold skew factor Average periodic refresh Interval Auto-Refresh to Active/Auto-Refresh command period Precharge-All (4 banks) command period Read preamble Read postamble Active bank A to Active bank B command ...
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ODT AC Electrical Characteristics Table 25 ODT AC Electrical Characteristics and Operating Conditions for DDR2-667 and DDR2-800 Symbol Parameter / Condition t ODT turn-on delay AOND t ODT turn-on AON t ODT turn-on (Power-Down Modes) AONPD t ODT turn-off ...
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Currents Specifications and Conditions I Table 27 Measurement Conditions DD Parameter Operating Current 0 t One bank Active - Precharge; CK between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. Operating Current 1 One bank ...
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I Table 27 Measurement Conditions (cont’d) DD Parameter Self-Refresh Current CKE ≤ 0.2 V; external clock off, CK and Other control and address inputs are FLOATING, Data bus inputs are FLOATING. All Bank Interleave Read Current ...
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I Table 29 Specification for HYS64T[32001/64020]HU–2.5–A DD Product Type Organization Symbol I DD0 I DD1 I DD2N I DD2P I DD2Q I DD3N I DD3P(MRS DD3P(MRS DD4R I DD4W I DD5B I DD5D I DD6 I ...
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I Table 30 Specification for HYS[64/72]T[32000/32001/64020]HU–3–A DD Product Type Organization 256MB x64 1 Rank –3 Symbol Max I 520 DD0 I 600 DD1 I 360 DD2N I 40 DD2P I 240 DD2Q I 360 DD3N I 150 DD3P(MRS ...
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I Table 31 Specification for HYS[64/72]T[32000/32001/64020]HU–3S–A DD Product Type Organization 256MB x64 1 Rank –3S Symbol Max I 500 DD0 I 570 DD1 I 360 DD2N I 40 DD2P I 240 DD2Q I 360 DD3N I 150 DD3P(MRS ...
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I Table 32 Specification for HYS[64/72]T[16000/32000/32001]HU–3.7–A DD Product Type Organization 128MB x64 1 Rank –3.7 Symbol Max I 220 DD0 I 240 DD1 I 140 DD2N I 20 DD2P I 100 DD2Q I 140 DD3N I 60 DD3P(MRS ...
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I Table 33 Specification for HYS[64/72]T[16000/32000/32001]HU–5–A DD Product Type Organization 128MB x64 1 Rank –5 Symbol Max I 200 DD0 I 220 DD1 I 110 DD2N I 20 DD2P I 80 DD2Q I 120 DD3N I 50 DD3P(MRS ...
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Currents Test Conditions I For testing the parameters, the following timing parameters are used. DD Table 34 I Measurement Test Conditions for PC2-5300 DD Parameter CAS Latency Clock Cycle Time Active to Read or Write delay Active to Active ...
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On Die Termination (ODT) Current The ODT function adds additional current consumption to the DDR2 SDRAM when enabled by the EMRS(1). Depending on address bits A[6,2] in the EMRS(1) a “weak” or “strong” termination can be selected. The Table ...
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... SPD Codes for PC2–6400U–666 Product Type Organization Label Code JEDEC SPD Revision Byte# Description 0 Programmed SPD Bytes in EEPROM 1 Total number of Bytes in EEPROM 2 Memory Type (DDR2) 3 Number of Row Addresses 4 Number of Column Addresses 5 DIMM Rank and Stacking Information 6 Data Width 7 Not used ...
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Table 37 SPD Codes for PC2–6400U–666 (cont’d) Product Type Organization Label Code JEDEC SPD Revision Byte# Description 17 Number of Banks on SDRAM Device 18 Supported CAS Latencies 19 DIMM Mechanical Characteristics 20 DIMM Type Information 21 DIMM Attributes 22 ...
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Table 37 SPD Codes for PC2–6400U–666 (cont’d) Product Type Organization Label Code JEDEC SPD Revision Byte# Description t 45 [ns] QHS.MAX 46 PLL Relock Time T Delta / ∆ CASE.MAX 4R4W 48 Psi(T-A) DRAM ∆ (DT0) ...
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Table 37 SPD Codes for PC2–6400U–666 (cont’d) Product Type Organization Label Code JEDEC SPD Revision Byte# Description 73 Product Type, Char 1 74 Product Type, Char 2 75 Product Type, Char 3 76 Product Type, Char 4 77 Product Type, ...
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... SPD Codes for PC2–5300U–444 Product Type Organization Label Code JEDEC SPD Revision Byte# Description 0 Programmed SPD Bytes in EEPROM 1 Total number of Bytes in EEPROM 2 Memory Type (DDR2) 3 Number of Row Addresses 4 Number of Column Addresses 5 DIMM Rank and Stacking Information 6 Data Width 7 Not used ...
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Table 38 SPD Codes for PC2–5300U–444 (cont’d) Product Type Organization Label Code JEDEC SPD Revision Byte# Description t 27 [ns] RP.MIN t 28 [ns] RRD.MIN t 29 [ns] RCD.MIN t 30 [ns] RAS.MIN 31 Module Density per Rank t t ...
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Table 38 SPD Codes for PC2–5300U–444 (cont’d) Product Type Organization Label Code JEDEC SPD Revision Byte# Description ∆ (DT3P slow) 3P.slow ∆ T (DT4R) / ∆ Sign (DT4R4W) 4R 4R4W ∆ (DT5B) 5B ∆ ...
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Table 38 SPD Codes for PC2–5300U–444 (cont’d) Product Type Organization Label Code JEDEC SPD Revision Byte# Description 81 Product Type, Char 9 82 Product Type, Char 10 83 Product Type, Char 11 84 Product Type, Char 12 85 Product Type, ...
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... SPD Codes for PC2–5300U–555 Product Type Organization Label Code JEDEC SPD Revision Byte# Description 0 Programmed SPD Bytes in EEPROM 1 Total number of Bytes in EEPROM 2 Memory Type (DDR2) 3 Number of Row Addresses 4 Number of Column Addresses 5 DIMM Rank and Stacking Information 6 Data Width 7 Not used ...
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Table 39 SPD Codes for PC2–5300U–555 (cont’d) Product Type Organization Label Code JEDEC SPD Revision Byte# Description t 26 SDRAM @ CL -2 [ns] AC MAX t 27 [ns] RP.MIN t 28 [ns] RRD.MIN t 29 [ns] RCD.MIN t 30 ...
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Table 39 SPD Codes for PC2–5300U–555 (cont’d) Product Type Organization Label Code JEDEC SPD Revision Byte# Description ∆ (DT3P fast) 3P.fast ∆ (DT3P slow) 3P.slow ∆ T (DT4R) / ∆ Sign (DT4R4W) 4R 4R4W ...
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Table 39 SPD Codes for PC2–5300U–555 (cont’d) Product Type Organization Label Code JEDEC SPD Revision Byte# Description 80 Product Type, Char 8 81 Product Type, Char 9 82 Product Type, Char 10 83 Product Type, Char 11 84 Product Type, ...
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... SPD Codes for PC2–4200U–444 Product Type Organization Label Code JEDEC SPD Revision Byte# Description 0 Programmed SPD Bytes in EEPROM 1 Total number of Bytes in EEPROM 2 Memory Type (DDR2) 3 Number of Row Addresses 4 Number of Column Addresses 5 DIMM Rank and Stacking Information 6 Data Width 7 Not used ...
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Table 40 SPD Codes for PC2–4200U–444 (cont’d) Product Type Organization Label Code JEDEC SPD Revision Byte# Description t 27 [ns] RP.MIN t 28 [ns] RRD.MIN t 29 [ns] RCD.MIN t 30 [ns] RAS.MIN 31 Module Density per Rank t t ...
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Table 40 SPD Codes for PC2–4200U–444 (cont’d) Product Type Organization Label Code JEDEC SPD Revision Byte# Description ∆ (DT3P slow) 3P.slow ∆ T (DT4R) / ∆ Sign (DT4R4W) 4R 4R4W ∆ (DT5B) 5B ∆ ...
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Table 40 SPD Codes for PC2–4200U–444 (cont’d) Product Type Organization Label Code JEDEC SPD Revision Byte# Description 81 Product Type, Char 9 82 Product Type, Char 10 83 Product Type, Char 11 84 Product Type, Char 12 85 Product Type, ...
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... SPD Codes for PC2–3200U–333 Product Type Organization Label Code JEDEC SPD Revision Byte# Description 0 Programmed SPD Bytes in EEPROM 1 Total number of Bytes in EEPROM 2 Memory Type (DDR2) 3 Number of Row Addresses 4 Number of Column Addresses 5 DIMM Rank and Stacking Information 6 Data Width 7 Not used ...
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Table 41 SPD Codes for PC2–3200U–333 (cont’d) Product Type Organization Label Code JEDEC SPD Revision Byte# Description t 27 [ns] RP.MIN t 28 [ns] RRD.MIN t 29 [ns] RCD.MIN t 30 [ns] RAS.MIN 31 Module Density per Rank t t ...
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Table 41 SPD Codes for PC2–3200U–333 (cont’d) Product Type Organization Label Code JEDEC SPD Revision Byte# Description ∆ T (DT4R) / ∆ Sign (DT4R4W) 4R 4R4W ∆ (DT5B) 5B ∆ (DT7 Psi(ca) ...
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Table 41 SPD Codes for PC2–3200U–333 (cont’d) Product Type Organization Label Code JEDEC SPD Revision Byte# Description 83 Product Type, Char 11 84 Product Type, Char 12 85 Product Type, Char 13 86 Product Type, Char 14 87 Product Type, ...
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Package Outlines Figure 10 Package Outline Raw Card A L-DIM-240-1 Data Sheet HYS[64/72]T[16/32/64]0xxHU-[2.5/.../5]-A Unbuffered DDR2 SDRAM Modules 66 Package Outlines Rev. 1.3, 2005-09 02182004-DHQB-4RRW ...
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Figure 11 Package Outline Raw Card C – L-DIM-240-3 Data Sheet HYS[64/72]T[16/32/64]0xxHU-[2.5/.../5]-A Unbuffered DDR2 SDRAM Modules 67 Package Outlines Rev. 1.3, 2005-09 02182004-DHQB-4RRW ...
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Figure 12 Package Outline Raw Card D L-DIM-240-8 Data Sheet HYS[64/72]T[16/32/64]0xxHU-[2.5/.../5]-A Unbuffered DDR2 SDRAM Modules 68 Package Outlines Rev. 1.3, 2005-09 02182004-DHQB-4RRW ...
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Figure 13 Package Outline Raw Card E L-DIM-240-9 Data Sheet HYS[64/72]T[16/32/64]0xxHU-[2.5/.../5]-A Unbuffered DDR2 SDRAM Modules 69 Package Outlines Rev. 1.3, 2005-09 02182004-DHQB-4RRW ...
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Figure 14 Package Outline Raw Card F L-DIM-240-6 Data Sheet HYS[64/72]T[16/32/64]0xxHU-[2.5/.../5]-A Unbuffered DDR2 SDRAM Modules 70 Package Outlines Rev. 1.3, 2005-09 02182004-DHQB-4RRW ...
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Figure 15 Package Outline Raw Card G L-DIM-240-7 Data Sheet HYS[64/72]T[16/32/64]0xxHU-[2.5/.../5]-A Unbuffered DDR2 SDRAM Modules 71 Package Outlines Rev. 1.3, 2005-09 02182004-DHQB-4RRW ...
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... 512 16 1) Multiplying “Memory Density per I/O” with “Module Data Width” and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall module memory density in MBytes as listed in column “Coding”. Constant Non-ECC Table 44 ECC Field Description ...
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Published by Infineon Technologies AG ...