m58bw016db STMicroelectronics, m58bw016db Datasheet - Page 56

• Manufacturer Part Number: m58bw016db
• Description: 16 Mbit 512kb X32, Boot Block, Burst 3v Supply Flash Memories
• Manufacturer: STMicroelectronics

Common Flash interface (CFI)
Appendix A
56/70
The common Flash interface is a JEDEC approved, standardized data structure that can be
read from the Flash memory device. It allows a system software to query the device to
determine various electrical and timing parameters, density information and functions
supported by the memory. The system can interface easily with the device, enabling the
software to upgrade itself when necessary.
When the CFI Query command (RCFI) is issued the device enters CFI Query mode and the
data structure is read from the memory.
show the addresses used to retrieve the data.
Table 26.
1. Offset 15h defines P which points to the primary algorithm extended query address table.
2. Offset 19h defines A which points to the alternate algorithm extended query address table.
Table 27.
1. The x 8 or Byte Address and the x 16 or Word Address mode are not available.
2. Query Data are always presented on DQ7-DQ0. DQ31-DQ8 are set to '0'.
Offset
P(h)
A(h)
1Bh
00h
01h
10h
27h
Address A0-A18
(1)
(2)
CFI Query identification string
System interface information
Device geometry definition
Primary algorithm-specific extended query
table
Alternate algorithm-specific extended query
table
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
Common Flash interface (CFI)
Query structure overview
CFI - query address and data output
Sub-section name
51h
52h
59h
M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB
Data
03h
00h
35h
00h
00h
00h
00h
00h
"Q"
"R"
"Y"
Table
Query ASCII String 52h; "R"
59h; "Y"
Primary vendor:
Command set and control interface ID code
Primary algorithm extended query address table:
P(h)
Alternate vendor:
Command Set and Control interface ID code
Alternate algorithm extended query address table
51h; "Q"
26,
Table
Manufacturer code
Device code
Command set ID and algorithm data offset
Device timing and voltage information
Flash memory layout
Additional information specific to the primary
algorithm (optional)
Additional information specific to the
alternate algorithm (optional)
(1)(2)
27,
Table
Instruction
28,
Description
Table 29
and
Table 30