m58bw032bb

Manufacturer Part Numberm58bw032bb
Description32 Mbit 1mb X32, Boot Block, Burst 3.3v Supply Flash Memory
ManufacturerSTMicroelectronics
m58bw032bb datasheet
 
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FEATURES SUMMARY
SUPPLY VOLTAGE
V
= 3.0V to 3.6V for Program, Erase
DD
and Read
V
= V
= 1.6V to 3.6V for I/O
DDQ
DDQIN
Buffers
HIGH PERFORMANCE
Access Time: 45, 55 and 60ns
75MHz Effective Zero Wait-State Burst
Read
Synchronous Burst Reads
Asynchronous Page Reads
MEMORY ORGANIZATION
– Eight 64 Kbit small parameter Blocks
– Four 128Kbit large parameter Blocks (of
which one is OTP)
– Sixty-two 512Kbit main Blocks
HARDWARE BLOCK PROTECTION
WP pin Lock Program and Erase
V
signal for Program/Erase Enable
PEN
SOFTWARE BLOCK PROTECTION
Tuning Protection to Lock Program and
Erase with 64-bit User Programmable
Password (M58BW032B version only)
SECURITY
64-bit Unique Device Identifier (UID)
FAST PROGRAMMING
Write to Buffer and Program capability
OPTIMIZED FOR FDI DRIVERS
Common Flash Interface (CFI)
Fast Program/Erase Suspend feature in
each block
LOW POWER CONSUMPTION
100µA Typical Standby
November 2004
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M58BW032BT, M58BW032BB
M58BW032DT, M58BW032DB
32 Mbit (1Mb x32, Boot Block, Burst)
3.3V Supply Flash Memory
Figure 1. Packages
LBGA80 (ZA)
10 x 8 ball array
ELECTRONIC SIGNATURE
Manufacturer Code: 20h
Top Device Code M58BW032xT: 8838h
Bottom Device Code M58BW032xB:
8837h
OPERATING TEMPERATURE RANGE
Automotive (Grade 3):
Industrial (Grade 6):
PRELIMINARY DATA
PQFP80 (T)
BGA
40 to 125°C
40 to 90°C
1/60

m58bw032bb Summary of contents

  • Page 1

    ... LOW POWER CONSUMPTION – 100µA Typical Standby November 2004 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. M58BW032BT, M58BW032BB M58BW032DT, M58BW032DB 32 Mbit (1Mb x32, Boot Block, Burst) 3.3V Supply Flash Memory Figure 1. Packages ...

  • Page 2

    ... Figure 3. LBGA Connections (Top view through package Figure 4. PQFP Connections (Top view through package Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Tuning Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 2. Top Boot Block Addresses, M58BW032BT, M58BW032DT . . . . . . . . . . . . . . . . . . . . . . 11 Table 3. Bottom Boot Block Addresses, M58BW032BB, M58BW032DB . . . . . . . . . . . . . . . . . . . 12 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Address Inputs (A0-A19 Data Inputs/Outputs (DQ0-DQ31 Chip Enable (E Output Enable (G) ...

  • Page 3

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Reset/Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 4. Asynchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Synchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Synchronous Burst Read Synchronous Burst Read Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 5. Synchronous Burst Read Bus Operations Burst Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Read Select Bit (M15 Standby Disable Bit (M14 X-Latency Bits (M13-M11 Y-Latency Bit (M9 Valid Data Ready Bit (M8) ...

  • Page 4

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Block Protection Status (Bit Tuning Protection Status (Bit 0 Table 11. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 MAXIMUM RATING Table 12. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 13. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 6. AC Measurement Input Output Waveform Figure 7. AC Measurement Load Circuit Table 14 ...

  • Page 5

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Figure 25.Unlock Device and Program a Tuning Protected Block Flowchart . . . . . . . . . . . . . . . . . 51 Figure 26.Unlock Device and Erase a Tuning Protected Block Flowchart . . . . . . . . . . . . . . . . . . . 52 Figure 27.Power-up Sequence to Burst the Flash Figure 28.Command Interface and Program Erase Controller Flowchart ( Figure 29.Command Interface and Program Erase Controller Flowchart ( Figure 30 ...

  • Page 6

    ... Kbits each. The large and small parameter blocks are located either at the top (M58BW032BT, M58BW032DT the bottom (M58BW032BB, M58BW032DB) of the address space. The first large parameter block is referred to as Boot Block and can be used either to store a boot code or parameters. The memory array orga- nization is detailed in Tables 2, Top Boot Block Ad- dresses and 3, Bottom Boot Block Addresses ...

  • Page 7

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Figure 2. Logic Diagram DDQ V DDQIN V PEN A0-A19 K L M58BW032BT E M58BW032BB RP M58BW032DT M58BW032DB SSQ Table 1. Signal Names A0-A19 Address inputs DQ0-DQ7 Data Input/Output, Command Input Data Input/Output, Burst Configuration DQ8-DQ15 Register DQ16-DQ31 Data Input/Output ...

  • Page 8

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Figure 3. LBGA Connections (Top view through package A15 A14 B A16 A13 C A17 A18 D DQ3 DQ0 E V DDQ DQ4 F V SSQ DQ7 G V DDQ DQ8 H DQ13 DQ12 J DQ15 DQ14 K V DDQIN RP 8/ PEN V SS ...

  • Page 9

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Figure 4. PQFP Connections (Top view through package) DQ16 1 DQ17 DQ18 DQ19 V DDQ V SSQ DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 12 DQ26 DQ27 V DDQ V SSQ DQ28 DQ29 DQ30 DQ31 M58BW032BT M58BW032BB 53 M58BW032DT M58BW032DB 41 DQ15 DQ14 DQ13 ...

  • Page 10

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Block Protection The M58BW032B features four different levels of block protection. The M58BW032D has the same block protection with the exception of the Tuning Block Protection, which is disabled in the factory. Write Protect Pin, WP, - When WP is Low the protection status that has been ...

  • Page 11

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Table 2. Top Boot Block Addresses, M58BW032BT, M58BW032DT # Size (Kbit) Address Range 73 128 FF000h-FFFFh 72 128 FE000h-FEFFFh 71 128 FD000h-FDFFFh 70 128 FC000h-FCFFFh 69 64 FB800h-FBFFFh 68 64 FB000h-FB7FFh 67 64 FA800h-FAFFFh 66 64 FA000h-FA7FFh 65 64 F9800h-F9FFFh 64 64 F9000h-F97FFh 63 64 F8800h-F8FFFh 62 64 F8000h-F87FFh 61 512 F4000h-F7FFFh ...

  • Page 12

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Table 3. Bottom Boot Block Addresses, M58BW032BB, M58BW032DB # Size (Kbit) Address Range 73 512 FC000h-FFFFFh 72 512 F8000h-FBFFFh 71 512 F4000h-F7FFFh 70 512 F0000h-F3FFFh 69 512 EC000h-EFFFFh 68 512 E8000h-EBFFFh 67 512 E4000h-E7FFFh 66 512 E0000h-E3FFFh 65 512 DC000h-DFFFFh 64 512 D8000h-DBFFFh 63 512 D4000h-D7FFFh 62 512 D0000h-D3FFFh 61 512 CC000h-CFFFFh ...

  • Page 13

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB SIGNAL DESCRIPTIONS See Figure 2., Logic Diagram and Names, for a brief overview of the signals connect this device. Address Inputs (A0-A19). The Address Inputs are used to select the cells to access in the mem- ory array during Bus Read operations either to read or to program data to ...

  • Page 14

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Enable Controlled Read or Write or Synchronous Burst Read operations. In Synchronous Burst Read operations the address is latched on the ac- tive edge of the Clock when Latch Enable is Low Once latched, the addresses may change IL without affecting the address used by the memory. ...

  • Page 15

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB BUS OPERATIONS Each bus operations that controls the memory is described in this section, see Tables Operations, for a summary. The bus operation is selected through the Burst Configuration Register; the bits in this register are described at the end of this section. On Power-up or after a Hardware Reset the mem- ory defaults to Asynchronous Bus Read and Asyn- chronous Bus Write ...

  • Page 16

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Asynchronous Latch Controlled Bus Write. Asynchronous Latch Controlled Bus Write opera- tions write to the Command Interface in order to send commands to the memory or to latch ad- dresses and input data to program. Bus Write op- erations are asynchronous, the clock don’t care during Bus Write operations ...

  • Page 17

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Synchronous Bus Operations For synchronous bus operations refer to Table together with the following text. Synchronous Burst Read. Synchronous Burst Read operations are used to read from the memo specific times synchronized to an external ref- erence clock. The valid edge of the Clock signal is the rising edge ...

  • Page 18

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Burst Configuration Register The Burst Configuration Register is used to config- ure the type of bus access that the memory will perform. The Burst Configuration Register is set through the Command Interface and will retain its informa- tion until it is re-configured, the device is reset, or the device goes into Reset/Power-Down mode ...

  • Page 19

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Table 6. Burst Configuration Register Bit Description M15 Read Select M14 Standby Disable (1) M13-M11 X-Latency M10 Reserved (2) M9 Y-Latency M8 Valid Data Ready M7-M4 Reserved M3 Wrapping M2-M0 Burst Length Note latencies can be calculated as the clock period), where t is the value given by the master microcontroller timing specifications. ...

  • Page 20

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Table 7. Burst Type Definition Starting Address Sequential 0 0 0-1-2 1-2-3 2-3-0 3-0-1 – – – – – 0-1-2 1-2-3 2-3-4 3-4-5 4-5-6 5-6-7 6-7-8 7-8-9- 8-9-10-11 20/60 x8 Sequential 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10.. 1-2-3-4-5-6-7-0 1-2-3-4-5-6-7-8-9-10-11.. 2-3-4-5-6-7-0-1 2-3-4-5-6-7-8-9-10-11-12.. 3-4-5-6-7-0-1-2 3-4-5-6-7-8-9-10-11-12-13.. 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10-11-2-13-14.. 5-6-7-0-1-2-3-4 5-6-7-8-9-10-11-12-13-14.. 6-7-0-1-2-3-4-5 6-7-8-9-10-11-12-13-14-15.. 7-0-1-2-3-4-5-6 7-8-9-10-11-12-13-14-15-16.. – 8-9-10-11-12-13-14-15-16-17.. 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10.. 1-2-3-4-5-6-7-8 1-2-3-4-5-6-7-8-9-10-11.. 2-3-4-5-6-7-8-9 2-3-4-5-6-7-8-9-10-11-12.. 3-4-5-6-7-8-9-10 3-4-5-6-7-8-9-10-11-12-13.. 4-5-6-7-8-9-10-11 4-5-6-7-8-9-10-11-12-13-14.. 5-6-7-8-9-10-11-12 5-6-7-8-9-10-11-12-13-14.. 6-7-8-9-10-11-12-13 6-7-8-9-10-11-12-13-14-15.. 7-8-9-10-11-12-13-14 7-8-9-10-11-12-13-14-15-16.. 8-9-10-11-12-13-14-15 8-9-10-11-12-13-14-15-16-17.. Continuous ...

  • Page 21

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Figure 5. Example Burst Configuration X-1-1 ADD VALID L DQ 3-1-1-1 DQ 4-1-1-1 DQ 5-1-1-1 DQ 6-1-1-1 DQ 7-1-1-1 DQ 8-1-1 VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID ...

  • Page 22

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB COMMAND INTERFACE All Bus Write operations to the memory are inter- preted by the Command Interface. Commands consist of one or more sequential Bus Write oper- ations. The Commands are summarized in 8., Commands. Refer to Table with the text descriptions below. Read Memory Array Command The Read Memory Array command returns the memory to Read mode ...

  • Page 23

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Typical Erase times are given in Table 10. See Appendix A, Figure 22., Block Erase Flow- chart and Pseudo Code, for a suggested flowchart on using the Block Erase command. Erase All Main Blocks Command The Erase All Main Blocks command is used to erase all 63 Main Blocks, without affecting the Pa- rameter Blocks ...

  • Page 24

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB The Status Register should be cleared before re- issuing the command. Program/Erase Suspend Command The Program/Erase Suspend command is used to pause a Program or Erase operation. The com- mand will only be accepted during a Program or Erase operation. It can be issued at any time dur- ing a program or erase operation. The command is ignored if the device is already in suspend mode ...

  • Page 25

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB The third write cycle re-issues the Tuning Protection Unlock Setup command (78h). The fourth write cycle inputs the second 32 bits of the code at address 00001h. Bit 7 of the Status Register should again be checked to verify that the device has successfully stored the second part of the code. When the de- vice is ready (b7 = ‘ ...

  • Page 26

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB specific block thus allowing program/erase opera- tions to this block, regardless of the WP pin status. Two bus operations are required to issue a Clear Block Protection Configuration Register com- mand: The first cycle writes the setup command The second write cycle specifies the address of the block to unprotect and confirms the command ...

  • Page 27

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Table 9. Read Electronic Signature Code Manufacturer M58BW032xT Device M58BW032xB Burst Configuration Register Block Protection Configuration Register Note version of the device. 2. BCR= Burst Configuration Register. 3. SBA is the start address of each block. Table 10. Program, Erase Times and Program Erase Endurance Cycles ...

  • Page 28

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB STATUS REGISTER The Status Register provides information on the current or previous Program, Erase, Block Protect or Tuning Protection operation. The various bits in the Status Register convey information and errors on the operation. They are output on DQ7-DQ0. To read the Status Register the Read Status Reg- ister command can be issued ...

  • Page 29

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB or erase command is issued, otherwise the new command will appear to fail. Program Suspend Status (Bit 2) The Program Suspend Status bit indicates that a Program operation has been suspended and is waiting to be resumed. The Program Suspend Status should only be considered valid when the Program/Erase Controller Status bit is set to ‘ ...

  • Page 30

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB MAXIMUM RATING Stressing the device above the ratings listed in ble 12., Absolute Maximum Ratings, may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicat the Operating sections of this specification is Table 12 ...

  • Page 31

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB DC AND AC PARAMETERS This section summarizes the operating and mea- surement conditions, and the DC and AC charac- teristics of the device. The parameters in the DC and AC characteristics Tables that follow, are de- rived from tests performed under the Measure- Table 13. Operating and AC Measurement Conditions ...

  • Page 32

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Table 15. DC Characteristics Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO (1) Supply Current (Random Read (1) Supply Current (Burst Read) I DDB (1) Supply Current (Standby) I DD1 (1) Supply Current (Program or Erase) I DD2 Supply Current (1) I DD3 (Erase/Program Suspend) ...

  • Page 33

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Figure 8. Asynchronous Bus Read AC Waveforms A0-A19 tAVQV tLLEL DQ0-DQ31 Table 16. Asynchronous Bus Read AC Characteristics. Symbol Parameter t Address Valid to Address Valid AVAV t Address Valid to Output Valid AVQV t Address Transition to Output Transition AXQX t Chip Enable High to Latch Enable Transition ...

  • Page 34

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Figure 9. Asynchronous Latch Controlled Bus Read AC Waveforms A0-A19 tAVLL L tLHLL E G DQ0-DQ31 Table 17. Asynchronous Latch Controlled Bus Read AC Characteristics Symbol Parameter t Address Valid to Latch Enable Low AVLL t Chip Enable High to Latch Enable Transition EHLX t Chip Enable High to Output Transition ...

  • Page 35

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Figure 10. Asynchronous Page Read AC Waveforms A0-A1 DQ0-DQ31 Table 18. Asynchronous Page Read AC Characteristics Symbol Parameter t Address Valid to Output Valid AVQV1 t Address Transition to Output Transition AXQX Note: For other timings see Table 16., Asynchronous Bus Read AC A0 and/or A1 tAVQV1 tAXQX OUTPUT ...

  • Page 36

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Figure 11. Asynchronous Write AC Waveform 36/60 ...

  • Page 37

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Figure 12. Asynchronous Latch Controlled Write AC Waveform 37/60 ...

  • Page 38

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Table 19. Asynchronous Write and Latch Controlled Write AC Characteristics Symbol Parameter t Address Valid to Latch Enable Low AVLL t Address Valid to Write Enable High AVWH t Data Input Valid to Write Enable High DVWH t Chip Enable Low to Latch Enable Low ELLL t Chip Enable Low to Write Enable Low ...

  • Page 39

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Figure 13. Synchronous Burst Read (Data Valid from ’n’ Clock Rising Edge) 39/60 ...

  • Page 40

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Table 20. Synchronous Burst Read AC Characteristics Symbol Parameter t Address Valid to Latch Enable Low AVLL Burst Address Advance High to Valid Clock t BHKH Edge Burst Address Advance Low to Valid Clock t BLKH Edge t Chip Enable Low to Latch Enable low ELLL t Output Enable Low to Output Valid ...

  • Page 41

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Figure 15. Synchronous Burst Read - Continuous - Valid Data Ready Output K (1) Output Note: Valid Data Ready = Valid Low during valid clock edge 1. V= Valid output. 2. The internal timing of R follows DQ. Figure 16. Synchronous Burst Read - Burst Address Advance ...

  • Page 42

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Figure 17. Reset, Power-Down and Power-up AC Waveform tVDHPH VDD, VDDQ Power-Up Table 21. Reset, Power-Down and Power-up AC Characteristics Symbol t Reset/Power-down High to Chip Enable Low PHEL (1) Reset/Power-down High to Output Valid t PHQV t Reset/Power-down High to Write Enable Low PHWL t Reset/Power-down High to Output Enable Low ...

  • Page 43

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB PACKAGE MECHANICAL Figure 18. LBGA80 10x12mm - 8x10 ball array, 1mm pitch, Bottom View Package Outline BALL "A1" A Note: Drawing is not to scale. Table 22. LBGA80 10x12mm - 8x10 ball array, 1mm pitch, Package Mechanical Data millimeters Symbol Typ ...

  • Page 44

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Figure 19. PQFP80 - 80 lead Plastic Quad Flat Pack, Package Outline QFP-B Note: Drawing is not to scale. Table 23. PQFP80 - 80 lead Plastic Quad Flat Pack, Package Mechanical Data millimeters Symbol Typ 2.800 23.200 D1 20.000 D2 18.400 e 0.800 E 17 ...

  • Page 45

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB PART NUMBERING Table 24. Ordering Information Scheme Example: Device Type M58 Architecture B = Burst Mode Operating Voltage 3.0V to 3.6V DDQ DDQIN Device Function 032B = 32 Mbit (x32), Boot Block, Burst Tuning Protection 032D = 32 Mbit (x32), Boot Block, Burst no Tuning Protection ...

  • Page 46

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB APPENDIX A. FLOW CHARTS Figure 20. Program Flowchart and Pseudo Code Start Write 40h Write Address & Data Read Status Register YES YES YES YES End Note error is found, the Status Register must be cleared before further P/E operations. ...

  • Page 47

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Figure 21. Program Suspend & Resume Flowchart and Pseudo Code Start Write B0h Write 70h Read Status Register YES YES Write FFh Read data from another block Write D0h Program Continues Program/Erase Suspend Command: – write B0h – ...

  • Page 48

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Figure 22. Block Erase Flowchart and Pseudo Code Start Write 20h Write Block Address & D0h Read Status Register YES YES YES b4 and YES YES End Note error is found, the Status Register must be cleared before further P/E operations. ...

  • Page 49

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Figure 23. Erase Suspend & Resume Flowchart and Pseudo Code Start Write B0h Write 70h Read Status Register YES YES Write FFh Read data from another block or Program Write D0h Erase Continues Program/Erase Suspend Command: – write B0h – ...

  • Page 50

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Figure 24. Unlock Device and Change Tuning Protection Code Flowchart Reset Device locked by tuning code Add: don't care Data: 78h Add: 00000h Data: First 32 bit Add: don't care Data: FFh Issue YES Read command Add: don't care ...

  • Page 51

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Figure 25. Unlock Device and Program a Tuning Protected Block Flowchart Reset Device locked by tuning code Add: don't care Data: 78h Add: 00000h Data: First 32 bit Add: don't care Data: FFh Issue YES Read command Add: don't care ...

  • Page 52

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Figure 26. Unlock Device and Erase a Tuning Protected Block Flowchart Reset Device locked by tuning code Add: don't care Data: 78h Add: 00000h Data: First 32 bit Add: don't care Data: FFh Issue YES Read command Add: don't care ...

  • Page 53

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Figure 27. Power-up Sequence to Burst the Flash Power-up or Reset Asynchronous Read Write 60h command Write 03h with A15-A0 BCR inputs Synchronous Read BCR bit 15 = '1' Set Burst Configuration Register Command: – write 60h – write 03h and BCR on A15-A0 ...

  • Page 54

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Figure 28. Command Interface and Program Erase Controller Flowchart (a) WAIT FOR COMMAND WRITE NO 90h YES READ ELEC. 98h SIGNATURE YES READ CFI ERASE COMMAND ERROR READ STATUS B 54/ 70h YES READ NO 20h STATUS YES ERASE 40h SET-UP YES ...

  • Page 55

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Figure 29. Command Interface and Program Erase Controller Flowchart ( 48h YES TP 78h PROGRAM SET_UP YES F TP UNLOCK SET_UP 60h YES NO FFh SET BCR SET_UP YES NO 03h YES D AI03836 55/60 ...

  • Page 56

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Figure 30. Command Interface and Program Erase Controller Flowchart ( YES READ STATUS READ ARRAY 56/60 YES ERASE SUSPENDED YES 70h NO YES PROGRAM 40h SET_UP NO NO YES READ D0h STATUS A ERASE YES READY NO NO READ B0h STATUS YES ERASE ...

  • Page 57

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Figure 31. Command Interface and Program Erase Controller Flowchart ( YES READ STATUS NO READ ARRAY PROGRAM YES READY PROGRAM SUSPEND YES READY PROGRAM READ SUSPENDED STATUS YES 70h NO YES READ D0h STATUS READ B0h STATUS YES NO AI03838 ...

  • Page 58

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Figure 32. Command Interface and Program Erase Controller Flowchart (e) 58/ PROGRAM YES NO READ READY STATUS UNLOCK YES NO READ READY STATUS AI03839 ...

  • Page 59

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB REVISION HISTORY Table 25. Document Revision History Date Version 20-Oct-2003 1.0 First Issue. Figure 7, AC Measurement Load Circuit modified. I 21-Oct-2003 1.1 Table 5, DC Characteristics. Bit M3 no longer reserved, described in 20-Nov-2003 1.2 text changes. Program and Erase Suspend Latency Times added to Table 10 ...

  • Page 60

    ... M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...