m58bw032bb STMicroelectronics, m58bw032bb Datasheet - Page 16

• Manufacturer Part Number: m58bw032bb
• Description: 32 Mbit 1mb X32, Boot Block, Burst 3.3v Supply Flash Memory
• Manufacturer: STMicroelectronics

M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Asynchronous Latch Controlled Bus Write.
Asynchronous Latch Controlled Bus Write opera-
tions write to the Command Interface in order to
send commands to the memory or to latch ad-
dresses and input data to program. Bus Write op-
erations are asynchronous, the clock, K, is don’t
care during Bus Write operations.
A valid Asynchronous Latch Controlled Bus Write
operation begins by setting the desired address on
the Address Inputs and pulsing Latch Enable Low,
V
mand Interface on the rising edge of Latch Enable,
Write Enable or Chip Enable, whichever occurs
first. Commands and Input Data are latched on the
rising edge of Chip Enable, E, or Write Enable, W,
whichever occurs first. Output Enable must remain
High, and Output Disable Low, during the whole
Asynchronous Bus Write operation.
See
Write
19., Asynchronous Write and Latch Controlled
Write AC
requirements.
Table 4. Asynchronous Bus Operations
Note: 1. X = Don’t Care
16/60
Asynchronous Bus Read
Asynchronous Latch
Controlled Bus Read
Asynchronous Page Read
Asynchronous Bus Write
Asynchronous Latch
Controlled Bus Write
Output Disable, G
Output Disable, GD
Standby
Reset/Power-Down
IL
. The Address Inputs are latched by the Com-
2. Data, Manufacturer Code, Device Code, Burst Configuration Register, Standby Status and Block Protection Configuration Register
Figure 12., Asynchronous Latch Controlled
Bus Operation
are read using the Asynchronous Bus Read command.
Characteristics, for details of the timing
AC
Waveform,
(2)
Address Latch
Read
Address Latch
Write
Step
and
V
V
V
V
V
V
V
V
V
V
E
X
IH
IL
IL
IL
IL
IL
IL
IL
IL
IL
Table
V
V
V
V
V
V
V
V
V
G
X
X
IH
IH
IH
IH
IH
IL
IL
IL
IL
Output Disable. The data outputs are high im-
pedance when the Output Enable, G, is at V
Output Disable, GD, is at V
Standby. When Chip Enable is High, V
Program/Erase Controller is idle, the memory en-
ters Standby mode, the power consumption is re-
duced to the standby level (I
Inputs/Outputs pins are placed in the high imped-
ance state regardless of Output Enable, Write En-
able or Output Disable inputs.
The Standby mode can be disabled by setting the
Standby Disable bit (M14) of the Burst Configura-
tion Register to ‘1’ (see
istics).
Reset/Power-Down. The memory is in Reset/
Power-Down mode when Reset/Power-Down,
RP, is at V
to the standby level (I
impedance, independent of the Chip Enable, E,
Output Enable, G, Output Disable, GD, or Write
Enable, W, inputs. In this mode the device is write
protected and both the Status and the Burst Con-
figuration Registers are cleared. A recovery time is
required when the RP input goes High.
GD
V
V
V
V
V
V
X
X
X
X
X
IH
IH
IH
IH
IH
IL
V
V
V
V
V
V
V
V
V
W
X
X
IH
IH
IH
IH
IH
IH
IL
IL
IL
IL
. The power consumption is reduced
RP
V
V
V
V
V
V
V
V
V
V
V
IH
IH
IH
IH
IH
IH
IH
IH
IH
IH
IL
V
V
V
V
V
V
X
X
X
X
X
L
DD1
IH
IH
IL
IL
IL
IL
Table 15., DC Character-
) and the outputs are high
Address
Address
Address
Address
Address
A0-A19
IL
.
X
X
X
X
X
X
DD1
) and the Data
Data Output
Data Output
Data Output
DQ0-DQ31
Data Input
Data Input
IH
High Z
High Z
High Z
High Z
High Z
High Z
, and the
IH
or