at45db021b ATMEL Corporation, at45db021b Datasheet - Page 12

• Manufacturer Part Number: at45db021b
• Description: At45db021b 2-megabit 2.7-volt Only Dataflash
• Manufacturer: ATMEL Corporation

5.5
6. Power-on/Reset State
12
Pin Descriptions
AT45DB021B
SERIAL INPUT (SI): The SI pin is an input-only pin and is used to shift data into the device. The
SI pin is used for all data input, including opcodes and address sequences.
SERIAL OUTPUT (SO): The SO pin is an output-only pin and is used to shift data out from the
device.
SERIAL CLOCK (SCK): The SCK pin is an input-only pin and is used to control the flow of data
to and from the DataFlash. Data is always clocked into the device on the rising edge of SCK and
clocked out of the device on the falling edge of SCK.
CHIP SELECT (CS): The DataFlash is selected when the CS pin is low. When the device is not
selected, data will not be accepted on the SI pin, and the SO pin will remain in a high-impedance
state. A high-to-low transition on the CS pin is required to start an operation, and a low-to-high
transition on the CS pin is required to end an operation.
WRITE PROTECT: If the WP pin is held low, the first 256 pages of the main memory cannot be
reprogrammed. The only way to reprogram the first 256 pages is to first drive the protect pin high
and then use the program commands previously mentioned. If this pin and feature are not uti-
lized it is recommended that the WP pin be driven high externally.
RESET: A low state on the reset pin (RESET) will terminate the operation in progress and reset
the internal state machine to an idle state. The device will remain in the reset condition as long
as a low level is present on the RESET pin. Normal operation can resume once the RESET pin
is brought back to a high level.
The device incorporates an internal power-on reset circuit, so there are no restrictions on the
RESET pin during power-on sequences. If this pin and feature are not utilized it is recommended
that the RESET pin be driven high externally.
READY/BUSY: This open-drain output pin will be driven low when the device is busy in an inter-
nally self-timed operation. This pin, which is normally in a high state (through a 1kΩ external
pull-up resistor), will be pulled low during programming operations, compare operations, and
during page-to-buffer transfers.
The busy status indicates that the Flash memory array and one of the buffers cannot be
accessed; read and write operations to the other buffer can still be performed.
When power is first applied to the device, or when recovering from a reset condition, the device
will default to SPI Mode 3. In addition, the SO pin will be in a high-impedance state, and a high-
to-low transition on the CS pin will be required to start a valid instruction. The SPI mode will be
automatically selected on every falling edge of CS by sampling the inactive clock state. After
power is applied and V
before an operational mode is started.
CC
is at the minimum datasheet value, the system should wait 20 ms
1937J–DFLSH–9/05