74ACT18823MTDX Fairchild Semiconductor, 74ACT18823MTDX Datasheet

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74ACT18823MTDX

Manufacturer Part Number
74ACT18823MTDX
Description
IC FLIP FLOP 18BIT D 3ST 56TSSOP
Manufacturer
Fairchild Semiconductor
Series
74ACTr
Type
D-Type Busr
Datasheet

Specifications of 74ACT18823MTDX

Function
Master Reset
Output Type
Tri-State Non Inverted
Number Of Elements
2
Number Of Bits Per Element
9
Frequency - Clock
100MHz
Delay Time - Propagation
2ns
Trigger Type
Positive Edge
Current - Output High, Low
24mA, 24mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
56-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
© 1999 Fairchild Semiconductor Corporation
74ACT18823SSC
74ACT18823MTD
74ACT18823
18-Bit D-Type Flip-Flop with 3-STATE Outputs
General Description
The ACT18823 contains eighteen non-inverting D-type flip-
flops with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. A buffered clock
(CP), Clear (CLR), Clock Enable (EN) and Output Enable
(OE) are common to each byte and can be shorted
together for full 18-bit operation.
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
FACT
Order Number
OE
CLR
EN
CP
I
O
Pin Names
0
–I
0
–O
n
n
n
is a trademark of Fairchild Semiconductor Corporation.
17
n
17
Output Enable Input (Active LOW)
Clear (Active LOW)
Clock Enable (Active LOW)
Clock Pulse Input
Inputs
Outputs
Package Number
MS56A
MTD56
Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
DS500294
Features
Connection Diagram
Broadside pinout allows for easy board layout
Separate control logic for each byte
Extra data width for wider address/data paths or buses
carrying parity
Outputs source/sink 24 mA
TTL-compatible inputs
Package Description
August 1999
Revised October 1999
www.fairchildsemi.com

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74ACT18823MTDX Summary of contents

Page 1

... O –O Outputs 0 17 FACT is a trademark of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation Features Broadside pinout allows for easy board layout Separate control logic for each byte Extra data width for wider address/data paths or buses carrying parity Outputs source/sink 24 mA ...

Page 2

Functional Description The ACT18823 consists of eighteen D-type edge-triggered flip-flops. These have 3-STATE outputs for bus systems organized with inputs and outputs on opposite sides. The device is byte controlled with each byte functioning identi- cally, but independent of the ...

Page 3

Absolute Maximum Ratings Supply Voltage ( Input Diode Current ( 0. 0. Output Diode Current ( 0. 0. Output ...

Page 4

AC Electrical Characteristics Symbol Parameter f Maximum Clock MAX Frequency t Propagation Delay PHL PLH Propagation Delay PHL CLR Output Enable Time PZL t PZH t Output Disable ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide Package Number MS56A 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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