s-24c02ci-t8t1u Seiko Instruments Inc., s-24c02ci-t8t1u Datasheet
s-24c02ci-t8t1u
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s-24c02ci-t8t1u Summary of contents
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... FT008-Z SNT-8A PH008-A TMSOP-8 FM008-A Caution This product is intended to use in general electronic devices such as consumer electronics, office equipment, and communications devices. Before using the product in medical equipment or automobile equipment including car audio, keyless entry and engine control unit, contact to SII is indispensable. 2 ...
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... GND 4 Figure 1 S-24C01CI-J8T1U S-24C02CI-J8T1U 8-Pin TSSOP Top view GND 4 5 Figure 2 S-24C01CI-T8T1U S-24C02CI-T8T1U 2 2 PROM Pin No. Symbol * VCC * SCL 4 GND *1 5 SDA SDA *1 6 SCL * VCC *1 ...
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... A2 SCL 4 GND SDA 5 SDA *1 6 SCL * VCC *1. All input pins have the CMOS structure. Do not set the input pins in high impedance during operation. Remark See Dimensions for details of the package drawings. Pin No. Symbol * VCC * ...
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... CMOS SERIAL E S-24C01C/02C Block Diagram SCL Start / Stop Detector SDA Device Address Comparator PROM Serial Clock Controller LOAD COMP LOAD INC Address Counter Y Decoder D OUT Figure 5 Seiko Instruments Inc. Rev.2.0 _00_C VCC WP GND Voltage Detector High-Voltage Generator ...
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... Input voltage Output voltage Operation ambient temperature Storage temperature Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. Recommended Operating Conditions Item Power supply voltage ...
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... CMOS SERIAL E S-24C01C/02C DC Electrical Characteristics Item Current consumption (READ) Item Current consumption (WRITE) Item Symbol Standby current I SB consumption Input leakage current I LI Output leakage current I LO Input current Input current Input Impedance Input Impedance Low level output voltage V ...
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... Bus release time Noise suppression time SCL t HD.STA t SU.STA SDA ( input ) SDA ( output ) 0.2 × 0.8 × less 0.3 × 0.7 × 100 pF Figure 6 Input / Output Waveform during AC Measurement Table 14 Symbol Min. f SCL t 1.3 LOW t 0.6 HIGH t 0 0.6 SU.STA t 0 ...
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... CMOS SERIAL E S-24C01C/02C Item Write time Start Condition SCL SDA t WS1 WP (valid WS2 (invalid PROM Table 15 V Symbol Min. − Acknowledgment Write data Signal D0 Figure 8 Write Cycle Timing Seiko Instruments Inc Unit Max. 5.0 ms Stop Condition ...
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... Wired-OR connection by pulling SCL (Serial Clock Input) Pin The SCL pin is used for the serial clock input. Since the signals are processed at a rising or falling edge of the SCL clock, pay attention to the rising and falling time and comply with the specification. ...
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... Every operation begins from a start condition. 2. Stop Condition Stop is identified by a low to high transition of the SDA line while the SCL line is stable at high. When a device receives a stop condition during a read sequence, the read operation is interrupted, and the device enters standby mode. ...
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... SDA 4. Acknowledge The unit of data transmission is 8 bits. During the 9th clock cycle period the receiver on the bus pulls down the SDA line to acknowledge the receipt of the 8-bit data. When an internal write cycle is in progress, the device does not generate an acknowledge. ...
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... The higher 4 bits of the device address are the “Device Code”, and are fixed to “1010”. In the S-24C01C/02C, successive 3 bits are the “Slave Address”. These 3 bits are used to identify a device on the system bus and are compared with the predetermined value which is defined by the address input pins (A2, A1, A0). ...
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... Rev.2.0 _00_C 6. Write 6. 1 Byte Write When the master sends a 7-bit device address and a 1-bit read / write instruction code set to “0”, following a start 2 condition, the E PROM acknowledges it. The E an acknowledge. After the E stop condition and that initiates the write cycle at the addressed memory. ...
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... In the S-24C01C/02C, the lower 4 bits of the word address are automatically incremented every time when the 2 E PROM receives 8-bit write data. If the size of the write data exceeds 16 bytes, the upper 4 bits of the word address remain unchanged, and the lower 4 bits are rolled over and the last 16-byte data that the S-24C01C/02C received will be overwritten. ...
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... WP pin changes during this time, the address data being written at this time is not guaranteed. Regarding the timing of write protection, refer to Figure 8. In not using the write protection, connect the WP pin to GND or set it open. The write protection is valid in the range of operation power supply voltage. ...
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... PROM does not generate an acknowledge, the write cycle is in progress and if the E generates an acknowledge, the write cycle has been completed recommended to use the read instruction “1” as the read / write instruction code transmitted by the master device. Acknowledge polling during write ...
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... Attention should be paid to the following point on the recognition of the address pointer in the E In the read operation the memory address counter in the E edge of the SCL clock for the 8th bit of the output data. In the write operation, on the other hand, the upper bits of the memory address (the upper bits of the word address and page address) incremented at the falling edge of the SCL clock for the 8th bit of the received data. ∗ ...
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... A dummy write is performed to load the memory address into the address counter. 2 When the E PROM receives a 7-bit device address and a 1-bit read / write instruction code set to “0” following a start condition, it responds with an acknowledge. responds with an acknowledge. The memory address is loaded to the address counter in the E operations ...
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... This is called “Sequential Read”. The master device outputs stop condition not an acknowledge, the reading of E Data can be read in succession in the sequential read mode. When the memory address counter reaches the last word address, it rolls over to the first word address. ...
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... Address Increment Timing The timing for the automatic address increment is the falling edge of the SCL clock for the 8th bit of the read data in read operation and the falling edge of the SCL clock for the 8th bit of the received data in write operation. ...
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... SCL pin with a pull-up resistor. As well, in case the SCL input pin of the E the tri-state output pin of the master device, connect the SCL pin with a pull-up resistor in order not to set it in high impedance. This prevents the S-24C01C/02C from error caused by an uncertain output (high impedance) from the tri- state pin when resetting the master device during the voltage drop ...
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... CMOS SERIAL E S-24C01C/02C WP A0, A1 PROM Figure 26 WP Pin Figure 27 A0, A1, A2 Pins Seiko Instruments Inc. Rev.2.0 _00_C ...
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... In the S-24C01C/02C, users are able to reset the internal circuit by inputting a start condition and a stop condition. Although the reset signal is input to the master device, the S-24C01C/02C’s internal circuit does not go in reset, but it does by inputting a stop condition to the S-24C01C/02C. The S-24C01C/02C keeps the same status thus cannot do the next operation ...
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... For example, if the power supply voltage is 5 must be raised within 200 ms. V (Max.) INIT * means there is no difference in potential between the VCC pin and the GND pin of the S-24C01C/02C. * the time required to initialize the S-24C01C/02C. No instructions are accepted during this time. INIT 24 ...
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... The voltage drops due to power off while the S-24C01C/02C is being accessed. Even if the master device is reset due to the low power voltage, the S-24C01C/02C may malfunction unless the power-on-clear operation conditions of S-24C01C/02C are satisfied. When not using this rise time seen in Figure 30 , adjust the phase (reset) to reset the internal circuit in the S- 24C01C/02C normally. 5.0 4 ...
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... CMOS SERIAL E S-24C01C/02C 5. 2 Initialization time The S-24C01C/02C initializes at the same time when the power supply voltage is raised. Input instructions to the S-24C01C/02C after initialization. S-24C01C/02C does not accept any instruction during initialization. Figure 31 shows the initialization time of the S-24C01C/02C. Initialization Time ...
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... The S-24C01C/02C may error if it does not recognize a start / stop condition correctly during transmission. In the S-24C01C/02C recommended to set the delay time of 0.3 µ s minimum from a falling edge of SCL for the SDA. This is to prevent S-24C01C/02C from going in a start / stop condition due to the time lag caused by the load of the bus line ...
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... Figure 34 Write Operation by Inputting Stop Condition during Write 9. Command cancel by start condition By a start condition, users are able to cancel command which is being input. However, adjust the phase while the S- 24C01C/02C is outputting “L” because users are not able to input a start condition. When users cancel the command, there may be a case that the address will not be identified ...
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... Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic protection circuit. ● SII claims no responsibility for any and all disputes arising out connection with any infringement of the products including this IC upon patents owned by a third party. ...
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... CMOS SERIAL E S-24C01C/02C Product Name Structure S-24C0xC I − xxxx PROM Package name (abbreviation) and IC packing specification J8T1 : 8-Pin SOP(JEDEC), Tape T8T1 : 8-Pin TSSOP, Tape I8T1 : SNT-8A, Tape K8T3 : TMSOP-8, Tape Fixed Product name S-24C01C : 1 Kbit S-24C02C : 2 Kbit Seiko Instruments Inc. ...
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... Use of the information described herein for other purposes and/or reproduction or copying without the express permission of Seiko Instruments Inc. is strictly prohibited. The products described herein cannot be used as part of any device or equipment affecting the human body, such as exercise equipment, medical equipment, security systems, gas equipment, or any apparatus installed in airplanes and other vehicles, without prior written permission of Seiko Instruments Inc ...