m29dw128g60nf6e Numonyx, m29dw128g60nf6e Datasheet - Page 17

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m29dw128g60nf6e

Manufacturer Part Number
m29dw128g60nf6e
Description
128-mbit 8 Mbit X16, Multiple Bank, Page, Dual Boot 3 V Supply Flash Memory
Manufacturer
Numonyx
Datasheet
M29DW128G
3.5
3.6
Table 4.
1. X = V
2. To write the four outermost parameter blocks (first two and last two), V
Bus Read
Bus Write
Standby
Output Disable
Reset
Operation
IL
or V
(1)
IH
During program or erase operations the memory will continue to use the program/erase
supply current, I
Reset
During reset mode the memory is deselected and the outputs are high impedance. The
memory is in reset mode when RP is at V
standby level, independently from the Chip Enable, Output Enable or Write Enable inputs.
Automatic standby
Automatic standby allows the memory to achieve low power consumption during read mode.
After a read operation, if CMOS levels (V
inactive for t
supply current is reduced to the standby supply current, I
characteristics). The data inputs/outputs will still output data if a bus read operation is in
progress.
The power supplier of data bus, V
circuits connected with data bus) when the memory enters automatic standby.
Bus operations
.
V
V
V
E
X
X
IH
IL
IL
AVQV
V
V
V
G
X
X
IH
IH
IL
CC3
+ 30 ns or more, the memory enters automatic standby where the internal
, for program or erase operations until the operation completes.
V
V
V
W
X
X
IH
IH
IL
RP
V
V
V
V
V
IH
IH
IH
IH
IL
CCQ
, can have a null consumption (depending on load
V
CC
PP
X
IL
X
X
X
X
(2)
/WP
. The power consumption is reduced to the
± 0.3 V) are used to drive the bus and the bus is
PP
/WP must be equal to V
Command address
Address inputs
Cell address
Address
A22-A0
CC2
X
X
(see
Table 22: DC
IH
.
Data inputs/outputs
Data output
DQ15-DQ0
Bus operations
Data input
Hi-Z
Hi-Z
Hi-Z
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