m29dw128g60nf6e Numonyx, m29dw128g60nf6e Datasheet - Page 41

• Manufacturer Part Number: m29dw128g60nf6e
• Description: 128-mbit 8 Mbit X16, Multiple Bank, Page, Dual Boot 3 V Supply Flash Memory
• Manufacturer: Numonyx

M29DW128G
Table 11.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. If an Entry Command Set command is issued, an Exit Protection Command Set command must be issued to return the device to read mode.
Exit Protection Command Set
PA program address, Ad address, BAd any address in the block, BKA bank address, RD read data, PWDn password word (n = 0 to 3), PWAn password address (n
= 0 to 3), X don’t care. All values in the table are in hexadecimal.
Grey cells represent read cycles. The other cells are write cycles.
DQ15 to DQ8 are ‘don’t care’ during unlock and command cycles. A22 to A16 are ‘don’t care’ during unlock and command cycles unless an address is required.
An enter command sequence must be issued prior to any operation. It disables read and write operations from and to block 0. Read and write operations from any
other block are allowed.
DATA = Extended block content.
Only one portion of password can be programmed or read by each Password Program command.
The password portion can be entered or read in any order as long as the entire 64-bit password is entered or read.
Protected and unprotected states correspond to 00 and 01, respectively.
The Clear all NVPBs command programs all NVPBs before erasure in order to prevent the over-erasure of previously cleared non-volatile modify protection bits.
Enter Lock Register
Command Set
Lock Register Program
Lock Register Read
Enter Password Protection
Command Set
Password Program
Password Read
Password Unlock
Enter Non-volatile Protection
Command Set
NVPB Program
Clear all NVPBs
Read NVPB Status
Enter NVPB Lock Bit
Command Set
NVPB Lock Bit Program
Read NVPB Lock Bit Status
Enter Volatile Protection
Command Set
VPB Program
Read VPB Status
VPB Clear
Enter Extended Block
Extended Block Program
Extended Block Read
Exit Extended Block
Command
Block protection commands
(4)
(4)
(4)
(8)
(9)
(7)
(6)(7)
(4)
(4)
(10)
3
2
1
3
2
4
7
3
2
2
1
3
2
1
3
2
1
2
3
2
1
4
2
(BKA)
(BKA)
BAd
BKA
BAd
555
555
555
555
555
555
555
Ad
00
00
Ad
X
X
X
X
X
X
X
X
X
X
1st
DATA
DATA
PWD0
RD(0)
RD(0)
RD(0)
Data
AA
AA
AA
AA
AA
AA
AA
A0
A0
A0
A0
A0
A0
A0
25
80
90
(5)
(5)
PWAn
(BKA)
(BKA)
(BKA)
2AA
2AA
2AA
BAd
2AA
2AA
BAd
BAd
2AA
2AA
(1)(2)(3)
Ad
00
PA
01
00
00
X
X
2nd
DATA
DATA
PWDn
PWD1
Data
55
55
03
55
00
30
55
00
55
00
01
55
55
00
(5)
(5)
(BKA)
(BKA)
555
555
555
555
555
555
555
Ad
02
00
3rd
Bus operations
PWD2
PWD0
Data
C0
E0
40
60
50
88
90
Ad
03
01
X
4th
PWD3
PWD1
Data
00
Ad
02
5th
PWD2 03 PWD3 00
Data
Command interface
Ad
6th
Data
Ad Data
7th
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