74LVX112SJ Fairchild Semiconductor, 74LVX112SJ Datasheet

IC FLIP FLOP DUAL JK LV 16SOP

74LVX112SJ

Manufacturer Part Number
74LVX112SJ
Description
IC FLIP FLOP DUAL JK LV 16SOP
Manufacturer
Fairchild Semiconductor
Series
74LVXr
Type
JK Typer
Datasheet

Specifications of 74LVX112SJ

Function
Set(Preset) and Reset
Output Type
Differential
Number Of Elements
2
Number Of Bits Per Element
1
Frequency - Clock
150MHz
Delay Time - Propagation
8.5ns
Trigger Type
Negative Edge
Current - Output High, Low
4mA, 4mA
Voltage - Supply
2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-SOIC (5.3mm Width), 16-SO, 16-SOEIIJ
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
© 2003 Fairchild Semiconductor Corporation
74LVX112M
74LVX112SJ
74LVX112MTC
74LVX112
Low Voltage Dual J-K Flip-Flops with Preset and Clear
General Description
The LVX112 is a dual J-K Flip-Flop where each flip-flop has
independent inputs (J, K, PRESET, CLEAR, and CLOCK)
and outputs (Q, Q). These devices are edge sensitive and
change states synchronously on the negative going transi-
tion of the clock pulse. Triggering occurs at a voltage level
of the clock and is not directly related to the transition time.
Clear and Preset are independent of the clock and are
accomplished by a low logic level on the corresponding
input. The J and K inputs can change when the clock is in
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Order Number
Package Number
MTC16
M16A
M16D
J
CLK
CLR
PR
Q
1
1
, J
Pin Names
, Q
1
, PR
1
2
1
, CLK
, K
, CLR
2
, Q
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
1
2
, K
1
, Q
2
2
2
2
DS012158
Data Inputs
Clock Pulse Inputs (Active Falling edge)
Direct Clear Inputs (Active LOW)
Direct Preset Inputs (Active LOW)
either state without affecting the flip-flop, provided that they
are in the desired state during the recommended setup and
hold times relative to the falling edge of the clock.
The inputs tolerate voltages up to 7V allowing the interface
of 5V systems to 3V systems.
Features
Description
Input voltage level translation from 5V–3V
Ideal for low power/low noise 3.3V applications
Package Description
October 1996
Revised December 2003
www.fairchildsemi.com

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74LVX112SJ Summary of contents

Page 1

... Ordering Code: Order Number Package Number 74LVX112M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74LVX112SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVX112MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “ ...

Page 2

Truth Table (h) HIGH Voltage Level L (l) LOW Voltage Level  X Immaterial HIGH-to-LOW Clock Transition Before HIGH-to-LOW Transition of Clock 0 0 Lower case letters indicate ...

Page 3

Absolute Maximum Ratings Supply Voltage ( Input Diode Current ( 0. Input Voltage ( Output Diode Current ( 0. 0. ...

Page 4

AC Electrical Characteristics V CC Symbol Parameter (V) t Propagation Delay 2.7 PLH PHL 3.3 t Propagation Delay 2.7 PLH CLR PHL n n ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number M16D 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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